Wednesday, March 31, 2010
Au etch rate
Hi,
Does anyone know the approximate etch rate for thick gold film using the standard Au etch solution?
Thanks,
Arash
----------------------------------------------------------------------------------
Arash Hazeghi
PhD Candidate
Stanford Center for Integrated Systems
CIS-X 300, 420 Via Palou Mall,
Stanford, CA 94305
phone: +1-650-725-0418
web: http://www.stanford.edu/~ahazeghi
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Tuesday, March 30, 2010
Re: Cr etchant: etching rate?
Thanks for letting us know about the expired Cr-14 etchant -- it should not have been in there and has now been replaced with current stock. The shelf-life is pretty short (3 months) so we need to keep an eye on it.
As for VLSI etchant etch rates, the Berkeley Microlab lab manual has an excellent reference that is linked on the wiki:
http://microlab.berkeley.edu/labmanual/chap1/JMEMSEtchRates2(2003).pdf
Please remember that the etch rates depend on film quality and that can vary depending on the machine and conditions of deposition. So the etch rates in this document should not be taken at full face value, but as a good starting point -- you should always verify etch rates against the actual film you are using in a critical etch. And so, yes, there is a delay in Cr etching because Cr is highly reactive and forms a native oxide on the surface which etches more slowly than bulk Cr.
Uli & Mary
Dany-Sebastien Ly-Gagnon wrote:
For the Cr etchant that we have in lab (Cr-14), the etch rate should be ~93nm/min from literature. Note that our Cr etchant is expired (since April 2009), so literature etch rates may not be reliable.
From experience, the etch seems to start only after ~30sec in solution, and the etch rate is quite fast. In about 1 min, I could etch 10nm Cr. It doesn't seem like the etch rate is linear in time and varies greatly (perhaps because it is expired), so it may undercut resist patterns significantly.
Best,
Dany
On Mon, Mar 29, 2010 at 10:27 AM, Kyunghoae Koo <koo1028@stanford.edu> wrote:
Dear Labmembers,
What is the etching rate of Cr etchant in snf? I need to etch 2nm buffer Cr layer. Lateral etching is not a big issue. How much time will be enough for that?
Thanks
Kyunghoae
===========================================================
Kyung-Hoae Koo
PhD candidate
Stanford University
EE department
e-Workshop: All-Spin Logic
All-Spin Logic
to be presented by Supriyo Datta, Behtash Behin-Aein and Kaushik Roy from the
Purdue University
on Tuesday, March 30th at 1pm. Stanford site for this tele-seminar
will be set up at Allen (CISX) 316X.
Abstract: The possible use of spin rather than charge as a state
variable in devices for processing and storing information has been
widely discussed, because it could allow low-power operation and might
also have applications in quantum computing. However, spin-based
experiments and proposals for logic applications typically use spin
only as an internal variable, the terminal quantities for each
individual logic gate still being charge-based. This requires repeated
spin-to-charge conversion, using extra hardware that offsets any
possible advantage.
We propose a spintronic device that uses spin at every stage of its
operation: information manipulation, transport, storage, input and
output are all accomplished with magnets and spin-coherent channels.
Contrary to the typical spin/magnet based logic schemes, the all-spin
scheme neither relies on ordinary magnetic fields (generated by
current carrying wires) nor does it rely on electrical read-out of
magnetic states. Binary data are represented by the bi-stable states
of nanomagnets (i.e. magnetic polarization) which can be non-volatile.
Application of a voltage signal to a magnetic contact (input data bit)
creates a spin-current in a channel which can be conveniently guided
and routed to another magnetic contact (output data bit) where it
determines its final state based on spin-torque phenomenon.
The all-spin device could potentially find use for low-power digital
logic since it should satisfy the five essential requirements for
logic applications namely nonlinearity, gain, concatenability,
feedback prevention and a complete set of Boolean operations.
Satisfaction of these essential characteristics paves the way for the
design of large scale digital circuits. Cascading and clocking of
logic gates will be discussed along with the
device/circuit/architecture co-optimization of all-spin logic (ASL).
While the focus of the talk will be on digital logic, it is
interesting to note that the all-spin scheme could provide a basis for
unconventional approaches. For example the spin accumulation in a
channel underneath a magnetic contact could provide a 'weighted
average' of different inputs that makes it switch ("fire") when it
exceeds a threshold like neural networks. Alternatively the magnetic
contacts on top of the channel could possibly serve as Input-Output
interface for spin-based quantum computing.
Biographies of Presenters:
Supriyo Datta received his B.Tech. from the IIT, Kharagpur in 1975,
his Ph.D from the University of Illinois, Urbana-Champaign in 1979 and
joined Purdue University in 1981. The approach pioneered by his group
for the description of quantum transport far from equilibrium has been
widely adopted in the field of nanoelectronics and he shared the IEEE
Cledo Brunetti award in 2002 with his colleague Mark Lundstrom. His
work has also influenced course and curriculum development in
nanoelectronics for which he received the IEEE Leon Kirchmayer award
for Graduate Teaching in 2008. URL:
http://cobweb.ecn.purdue.edu/~datta/
Behtash Behin-Aein received his B.Sc. in electrical engineering from
Purdue University, West Lafayette, IN in 2004. He is currently a
research assistant in Supriyo Datta's research group working towards
his Ph.D at Purdue University. His research interests include spin
devices, spin dynamics in confined magnetic structures, spin transport
and spin-torque phenomenon.
Kaushik Roy received his B.Tech. degree in electronics and electrical
communications engineering from IIT, Kharagpur, India, and Ph.D in
electrical and computer engineering from the University of Illinois at
Urbana- Champaign in 1990. His research interests include VLSI
design/CAD for nano-scale Silicon and non-Silicon technologies,
low-power electronics for portable computing and wireless
communications, VLSI testing and verification, and reconfigurable
computing. Dr. Roy has received the National Science Foundation Career
Development Award in 1995, IBM faculty partnership award, ATT/Lucent
Foundation award, 2005 SRC Technical Excellence Award, SRC Inventors
Award and Purdue College of Engineering Research Excellence Award.
URL: https://engineering.purdue.edu/NRL
Monday, March 29, 2010
RSVP NOW: Are there academics outside of academia? An MSE alumni's perspective of life at a startup
In McCullough Bldg. Rm. 115
Starts at 5:00pm
Section Manager of Print Integration
RSVP below by 3/30 for complimentary dinner and a chance to win door prizes!
If you have trouble viewing or submitting this form, you can fill it out online:
http://spreadsheets.google.com/viewform?formkey=dHcyYnY1N255dTk3ZFJRMndHMDVNWVE6MA
Getting ready for the next Coral release ....
Within the next couple of days, we will be releasing a new version of
Coral that will require use of Java Version 6 instead of Java Version
5. Why? Java 5 has reached its End of Service Life and is less
supportable than the current version (Java Version 6). More
importantly, new Coral capabilities will likely use features that are
available only in newer versions of Java. For example, people have
suggested that we be able to open xReporter from within Coral and have
also suggested that links to online documentation be available from
within Coral. Both of those features will be available in the new
release, but require a feature that is only available in Java 6 ... the
ability to open the default browser from within a Java application.
How can you prepare? If you already have Java 6 on your machine, you
are ready to go and do not have to do anything. If you have Java 5,
however, you will want to download and install the Java 6 runtime
environment. How can you tell? If you are on a Windows machine, you
can open the "Run ..." command line window from the Start Menu and type
in the command:
javaws -viewer
This will open the Java Web Start cache viewer which will open two
windows: one named Java Cache Viewer and the other named Java Control
Panel. When those open, close the Java Cache Viewer and then click the
Java tab on the Java Control Panel. On that panel, there should be a
button named "View" that will show you a list of one or more versions of
Java currently installed on your machine. You may have several, but you
are looking for one that is listed as Platform = 1.6 (which is Java 6).
If you only have Platform = 1.5 entries, then you only have Java 5 and
will need to download and install a Java 6 runtime environment.
If you need to do that go to:
http://java.sun.com/javase/downloads/index.jsp
On that page there are a number of red buttons that say "Download" ...
but there will be only one button that says "Download JRE"
If you click that link, you will be able to download and install the
Java Runtime Enviroment onto your machine. That version will run the
existing version of Remote Coral but will also be what you need when we
release the new version of Java later this week.
Note: if you are on a Linux, Solaris, or Mac OS X platform, you can
easily tell what version of Java you are running by opening a command
line window and issuing the command: 'java -version'.
Let me know if you have any questions,
John
Re: Cr etchant: etching rate?
From experience, the etch seems to start only after ~30sec in solution, and the etch rate is quite fast. In about 1 min, I could etch 10nm Cr. It doesn't seem like the etch rate is linear in time and varies greatly (perhaps because it is expired), so it may undercut resist patterns significantly.
Best,
Dany
Dear Labmembers,
What is the etching rate of Cr etchant in snf? I need to etch 2nm buffer Cr layer. Lateral etching is not a big issue. How much time will be enough for that?
Thanks
Kyunghoae
===========================================================
Kyung-Hoae Koo
PhD candidate
Stanford University
EE department
Cr etchant: etching rate?
Dear Labmembers,
What is the etching rate of Cr etchant in snf? I need to etch 2nm buffer Cr layer. Lateral etching is not a big issue. How much time will be enough for that?
Thanks
Kyunghoae
===========================================================
Kyung-Hoae Koo
PhD candidate
Stanford University
EE department
Sunday, March 28, 2010
FW: ME260 - Fuel cell science and technology
FYI
From: Rainer Fasching [mailto:rfasch@stanford.edu]
Sent: Saturday, March 27, 2010 2:23 PM
To: Mary Tang
Subject: FW: ME260 - Fuel cell science and technology
Dear Mary:
I’m teaching ME260 course this spring quarter. The announcement was placed delayed on the bulletin and I want to make sure that students are aware of this course opportunity. I would appreciate it very much, if you could forward this email to SNF students/colleagues.
Thanks,
Rainer Fasching
ME260
Fuel Cell Science and Technology
Spring 2010
Tuesday, Thursday 4:15pm-5:30pm
Lane History Corner (Bldg 200), Room 305
Audience: Targeted at advanced undergraduate or beginning level graduate students in the engineering or physical sciences. We anticipate diverse student backgrounds and furthermore recognize that the electrochemical concepts will be new to most students. Therefore, the material will be presented assuming no prior background in electrochemistry. Much of the material covered will be theoretical and fundamental in nature.
Description: Fuel cells provide one of the most efficient means for converting the chemical energy stored in a fuel to electrical energy. Fuel cells offer improved energy efficiency and reduced pollution compared to heat engines. While composed of no (or very few) moving parts, a complete fuel cell system amounts to a small chemical plant for the production of power. This course introduces students to the fundamental aspects of fuel cell systems, with emphasis placed on proton exchange membrane (PEM) and solid oxide fuel cells (SOFC). Students will learn the basic principles of electrochemical energy conversion while being exposed to relevant topics in materials science, thermodynamics, and fluid mechanics.
Outline:
Fuel Cell Principles
What is a Fuel Cell?
Fuel Cell Thermodynamics
Fuel Cell Kinetics
Fuel Cell Charge Transport
Diffusion and Mass Transport
Fuel cell Modeling
Fuel cell Characterization
Fuel Cell Technology
Fuel cell Types
Fuel cell Stacking
Fuel cell Systems
Fuel cell Applications
Objectives: By the end of the course, students will have gained the skills and knowledge to demonstrate the following objectives:
· Fuel Cell Characteristics. Contrast the advantages and disadvantages of fuel cells to other energy conversion technologies (e.g. heat engines). Discuss the advantages and disadvantages between the various fuel cell types (SOFC, MCFC, PAFC, AFC, PEMFC).
· Fuel Cell Thermodynamics. Perform thermodynamic calculations to quantitatively predict ideal fuel cell voltages as a function of gas concentrations, pressure, and temperature. Calculate thermodynamic efficiencies. Perform heat and mass balances on fuel cell systems. Describe the basic mechanisms of fuel cell reactions, electron transfer, and ionic transport at the molecular scale.
· Fuel Cell Kinetics. Derive equations for activation, IR, and concentration losses in fuel cell systems. Assemble a complete (simple) analytical model for a fuel cell system and use it to predict fuel cell performance over a range of operating conditions (e.g. at various temperature, pressures, feed rates, etc.) Identify the most significant kinetic constraints that limit current fuel cell performance and suggest research directions to improve performance.
· Fuel Cell Research. Identify the major materials issues remaining in fuel cell design. Describe the most important characterization techniques used to test fuel cell performance and identify bottlenecks.
· Fuel Cell Systems. Describe the major strategies for fuel cell stacking. Compare planar vs. vertical fuel cell interconnection. Discuss the major fuel cell system applications (portable, transportation, stationary power) and be able to argue which fuel cell types are most suited for each application. Discuss and describe the ancillary equipment necessary for a complete fuel cell system (Compressors, humidification, reformers, heat management, power conditioning). Perform a basic economic analysis to predict the cost reductions necessary such that fuel cell systems can be economically competitive with current energy conversion technologies.
Rainer Fasching, PhD
Cons. Associate Professor
Department of Mechanical Engineering
Stanford University
Mail: 440 Escondido Mall, Bldg. 530, Rm. 220, Stanford, CA 94305-3030
Email: rfasch@stanford.edu
Phone: 415-505-3385
Fax: 650-723-5034
Saturday, March 27, 2010
Comment p5000etch SNF 2010-03-27 11:23:37: Chamber C..
leybold D65. I need to look for some hardweres(clamp, bellow
and adaptor) to convert..
Comment p5000etch SNF 2010-03-27 11:18:58: Chamber A He leak
I noticed the backside only happened on the last step of
the recipe which is purge step and it don't require a he cooling
edited the last recipe step (purge) to no backside he..
Re: Problem p5000etch SNF 2010-03-25 13:57:03: He leak update
it turn on the final he valve..
Friday, March 26, 2010
Comment p5000etch SNF 2010-03-26 17:47:48: Ch A Helium leak rate too high
It is stopping the process midway.
Comment p5000etch SNF 2010-03-26 16:38:28: Chamber C
replacement D65 pump..
Problem p5000etch SNF 2010-03-26 04:17:02: Ch. C is in fault mode (red)
Thursday, March 25, 2010
SNF Personal Chemicals in Flammables Storage
Because of space and organizational concerns, storage class L personal
chemicals are being moved from the Flammables cabinets in epi2 area out
to the service area where there is a nice, new flammables cabinet. The
plan is to keep all personal-use chemicals in this new cabinet. The two
Flammables cabinets in the epi2 area will be dedicated to SNF-supplied
chemicals. This means we will be able to stock more high-use chemicals
-- and hopefully avoid running out of Remover PG over a busy weekend.
If you have personal-use chemicals in the Flammables cabinets, please
take a few minutes to make sure they are dated. If they are no longer
in use, please dispose of them. If new yellow labels are needed,
contact Mahnaz or other staff to get new ones. Outdated and unlabeled
chemicals are subject to removal from the lab.
Any questions, please contact the....
Litho team
3/25/10
Dedicated Wafer Cassette use in SNF
It has been brought to our attention that some people need to be reminded of the policies on dedicated cassettes:
1. No litho cassettes may be taken into the white area of the lab. This includes the metal boats as well as the teflon cassettes with brown buttons.
2. No Furnace preclean or etch cassettes from clean or semiclean stations may be taken into the Litho area of the lab. This includes metal cassettes.
3. To move wafers between the white and litho areas of the lab, use your own transfer cassettes.
4. If you remove a dedicated cassette from a station (for example, from wbdiff to a furnace for loading) return it as soon as possible.
These policies are covered in wet bench training at all these stations. If you need a refresher, refer to the training materials in the website (procedures on the wiki, video at http://spf.stanford.edu/training/wbdiff.wmv.) If everyone is diligent about proper cassette use, the cleanliness in the lab can be better maintained and there should be sufficient cassettes for everyone's use. If you see someone improperly using dedicated cassettes, you have every right to correct that person. You may also report to staff (please provide specific details.)
Thanks for your attention --
Your SNF Staff
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu
Problem p5000etch SNF 2010-03-25 13:57:03: He leak update
It appears the helium leak rate is not calculated until 10sec into the etch step where the valve is opened. If there is a leak problem the error happens and stops the etch at this point. It would be better if the leak rate was checked prior to etch step, so error would not happen after 10sec of the etch step.
Comment p5000etch SNF 2010-03-25 13:54:58: etch rate problem resolved
Wednesday, March 24, 2010
Problem p5000etch SNF 2010-03-24 12:39:01: ch.B etch rate unstable
350-400 nm/min
batch 1: jimox, 30sec
wafer1: 309 nm/min
wafer2: 280 nm/min
wafer3: 120 nm/min !!!
batch2: jimox, 30sec
wafer1: 289
wafer2: 292
wafer3: 110 !!!
batch3: jimox, 140sec
wafer1: 278
wafer2: ~154
wafer3: ~210
wafer4: ~160
wafer5: ~101
wafer6: ?
wafer7: >231
wafer8: 300
Observations during run:
RF power and all gases were very close to setpoint. He leak was <2sccm, looked at for every wafer. No rotation of any wafer after run.
Gas flow values did not fluctuate at all during run. Each were at +2sccm from setpoint, and stayed at this value exactly for the whole run. Typically they fluctuate, which might mean they are not being read properly.
EPD also showed very strange drops and rises at random times. This might be due to gasses turning on and off intermitently.
Tuesday, March 23, 2010
Re: please be careful with chemicals
| This cannot be stressed enough. I encountered trace amounts, but enough to get an HF burn while working @ SJSU's IC lab. Be careful with that stuff. Roy --- On Tue, 3/23/10, Shrestha Basu Mallick <shresbm@gmail.com> wrote:
|
please be careful with chemicals
Someone had put the 6:1 BOE where the hydrogen peroxide should have been. Its a risky mistake especially because both have white caps
--
Shrestha
Ganesh Sundaram of Cambridge Nanotech speaking about atomic layer deposition in SNF Wednesday March 24, 2010
a reminder that Ganesh Sundaram the VP of Technology for Cambridge Nanotech will be visiting Stanford on March 24, 2010. as many of you know SNF and Cambridge Nanotech have partnered on a getting a new plasma optional, dual chamber ALD system (a Fiji F202) installed at SNF. this system will be delivered to SNF in early April 2010 and Ganesh has agreed to speak with labmember community at 11am-noon in allen 101x (formerly cis 101x) about the system and capabilities that will very soon be available to our users. In addition, Ganesh will be available for questions concerning the system. I hope many of you can make this talk as it will be highly informative and will allow you to get a jump start on utilizing a wonderful new addition in terms of capability and capacity for our fab and its users.
if there are any questions i can answer in advance, please let me know.
j
Monday, March 22, 2010
Alumni Careers Seminar on 4/1 - Aditi Chandra presents her perspective of life at a startup
In McCullough Bldg. Rm. 115
Starts at 5:00pm
Section Manager of Print Integration
Kovio Inc. (a printed electronics startup)
RSVP below by 3/30 for complimentary dinner and a chance to win door prizes!
If you have trouble viewing or submitting this form, you can fill it out online:
http://spreadsheets.google.com/viewform?formkey=dHcyYnY1N255dTk3ZFJRMndHMDVNWVE6MA
Re: Shutdown p5000etch SNF 2010-03-20 10:21:39: Working on robot alignment...
status for now, still need to address the robot extension
problem. The wafer on pocket blade position is repeatable
i'm not seeing the wafer rotating on the pokcet after the
adjustement and fixing the load lock isolation problem.
Comment p5000etch SNF 2010-03-22 13:40:31: Update:
vibration problem. Adjusted clamping force and release
clamp position sensor. Set the robot extension speed
from 4 to 10 help compensate on the virbration during
extension load and unload sequence, currently running
cha B jim-ox recipe and so far wafer on blade pocket is
not rotating when robot extension is moving..
Mini flashlights at etch and deposition tools ....
Thanks to recommendations from Jim Kruger, we've now distributed a
number of small LED flashlights at a variety of etch and deposition
tools where they will, hopefully, be useful for illuminating wafers
through view ports.
Hopefully this will reduce the number of times when you cannot find a
working flashlight when you need one or have to appropriate one from
another tool. Also, the clear case will make it easier to notice that a
flashlight is still on so that we will, hopefully, go through fewer
batteries.
Happy processing,
John
Process Clinic today: Monday, 3/22, 2 pm
Greetings labmembers -- Just a reminder that there is a Process Clinic today (Monday) from 2-4 pm in the cubicle area outside of Maureen's office. Staff and senior labmembers will be on hand to answer questions and brainstorm ideas to address process issues. Bring your ideas, process questions, your process runsheets, SpecMat request, device layouts, and whatever else. Your SNF staff
Sunday, March 21, 2010
Furnace at 180 C
Dear Labmembers,
Does anybody know if there is any furnace I can use, compatible with gold and constant temperature at 180 C in an inert gas ambient? Fga2 seems to be unstable at low temperature below 300C. I may not adjust the temperature of singe oven. Is there any?
Thank you
Kyunghoae
===========================================================
Kyung-Hoae Koo
PhD candidate
Stanford University
EE department
Comment p5000etch SNF 2010-03-21 21:35:26: Update
is 1.5sccm he leak with clamping force at almost max down.
we may need to change the spring on the cathode assembly?
Also changed the silt door actuator valve from our spare but
is also bad (intermittently will not open), re-installed
original actualtor valve., will continue working on the problem
tomorrow..
Ganesh Sundaram of Cambridge Nanotech speaking about atomic layer deposition in SNF Wednesday March 24, 2010
Ganesh Sundaram the VP of Technology for Cambridge Nanotech will be visiting Stanford on March 24, 2010. as many of you know SNF and Cambridge Nanotech have partnered on a getting a new plasma optional, dual chamber ALD system (a Fiji F202) installed at SNF. this system will be delivered to SNF in early April 2010 and Ganesh has agreed to speak with labmember community at 11am-noon in allen 101x (formerly cis 101x) about the system and capabilities that will very soon be available to our users. In addition, Ganesh will be available for questions concerning the system. I hope many of you can make this talk as it will be highly informative and will allow you to get a jump start on utilizing a wonderful new addition in terms of capability and capacity for our fab and its users.
if there are any questions i can answer in advance, please let me know.
j
Saturday, March 20, 2010
Comment p5000etch SNF 2010-03-20 15:51:00: Update..
to much play during extension transfer and at the same time
also causing the wafer in the blade pocket to moved and intermittently
rotate. Also, we a have problem with chamber B slit door actuator
valve it intermttiently opened to fast causing it slammed down creating
vibration causing the wafer on chamber B to moved, i'm currently
working on all this problem...
Friday, March 19, 2010
Comment p5000etch SNF 2010-03-19 15:10:01: Update wafer did not drop
- Need to rebuild the load lock vacuum valve.
- Ch.A and C are runable but there is a good chance that the wafer might shift during the unload. Please run it only when staff or a super user is available to recover the wafer.
-Ch.B is down. It seems to be more sensitive to the vibrations.
Re: Problem p5000etch SNF 2010-03-17 18:23:14: wafer exploded in Ch.A
Found Gloves on the Bench Outside the Cleanroom
Dear Labmembers,
A concerned Staff member found some “Saranac” gloves on the bench outside the cleanroom. If these gloves are yours, please come and claim them from me.
I sit in cubicle # 41 on the first floor.
Maureen
Maureen Baran
Stanford Nanofabrication Facility
Lab Services Administrator
mbaran@stanford.edu
650-725-3664
FW: [CPN] NanoDays - Volunteers needed
Dear All - The Center for Probing the Nanoscale, in collaboration with the Stanford Nanofabrication Facility, is hosting 50 students from the Girls Middle School in Mountain View on March 31st as part of the nationwide initiative to bring nanoscience and nanotechnology awareness to the public. The students will spend some time at SNF in the morning and then come over to GLAM for hands-on activities relating to nano.
I am looking for 8 volunteers to help with the hands-on activities. Activities will be offered from March 31, 11:00-12:15. If your schedule permits, volunteers are also invited to a pizza lunch with the students.
Please send me an email (tobi@stanford.edu) if you can help in making this day a memorable and exciting day for our visitors!
Thanks,
TOBI
Tobias Beetz, Ph.D.
Associate Director, Center for Probing the Nanoscale, Stanford University
McCullough Bldg. (126B), 476 Lomita Mall, Stanford, CA 94305-4045, Phone: 650-723-4490
Wednesday, March 17, 2010
Problem p5000etch SNF 2010-03-17 21:53:14: Ch. B high He leak rates
Problem p5000etch SNF 2010-03-17 18:23:14: wafer exploded in Ch.A
Re: Problem p5000etch SNF 2010-03-16 18:50:40: Ch. A down
Commercializing Technology through the Power of IP Licensing
I wanted to let you and your students know about an exceptional intellectual property-related educational opportunity. Below is the description for the "PDS 100: Commercializing Technology through the Power of IP Licensing" course that is being hosted by OTL on April 26th. For a special rate, students will receive course instruction, hands-on negotiation experience, both breakfast and lunch, a networking reception, and a ONE- YEAR STUDENT MEMBERSHIP TO LES for only $35.
Thanks,
Linda
To view this email as a web page, go here
Around the World with LES
April 26th at Participating Chapters
LES (USA & Canada) is pleased to announce Around the World with LES, a series of coordinated events on April 26th, held in conjunction with World Intellectual Property Organization's (WIPO) World IP Day. Participating local chapters will host educational and social functions with the objective of bringing together members of the IP, licensing and business development community to celebrate the advancement of IP commerce. More Info.
LES Silicon Valley Chapter
PDS 100: Commercializing Technology through the Power of IP Licensing
A dynamic one-day professional development course
(Approved for 7 hours of general CA CLE credit)
DATE & TIME
Monday, April 26, 2010
8:30 AM - 5:30 PM
LOCATION
Stanford University
Oak West Lounge, 2nd floor of Tresidder Memorial Union Stanford, CA
Map
HOST & SPONSOR
REGISTRATION FEE
(includes breakfast, lunch & networking reception):
LES Members and Non-Members: $195
University/Government: $125
LES Student Member: $25
Non-Member Student: $35*
*The fee includes one year LES (USA & Canada) student membership.
DESCRIPTION
There is more emphasis now than ever before on commercialization, company formation and job creation from the billions of dollars invested annually in research and development at America's universities, government laboratories and small businesses. Whether you are an entrepreneur in the making, a principal investigator or student (at any level) who wants a better grasp of the basics, or an aspiring technology transfer professional, this course will give you the tools you need to understand and participate effectively in the process of protecting IP and facilitating its commercialization. Join us for this interactive one-day course for:
- IP Basics: patents, trademarks, know-how, trade secrets and more
- Smart strategies for creating, organizing, managing and securing IP assets
- Bringing IP to market - Commercialization
- Royalties and ideas for maximizing IP value and making money!
- Interesting case studies and an interactive deal negotiation by participants Click here for more information and online registration
PDS 100 COURSE CONTACT
Linda Chao
LES Silicon Valley Chapter Education Chair
les-svcpds100@otlmail.stanford.edu
Space is limited so register early!! Registration deadline is Friday,
April 16, 2010. No on-site registrations.
Join LES Now
In honor of its 45th Anniversary, LES is offering new members who join before March 31st a $45 discount on their 2010 dues, a $25 gift card and complimentary attendance at a local LES chapter event - all as an added bonus to the valuable resources and networking you'll get from your new involvement in LES!
JOIN NOW by applying online at lesusacanada.org/join and use the promo code 45MATW.
About LES
Since 1965, LES (USA & Canada) has been the leading association for professionals engaged in the transfer, use, development, commercialization and marketing of intellectual property.
LES (USA & Canada) is a member society of the Licensing Executives Society International, Inc. (LESI), with a worldwide membership of nearly 11,000 members in 32 national societies, representing over 90 countries.
Click here to view our membership brochure.
© 2010 Licensing Executives Society. All rights reserved
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Tuesday, March 16, 2010
Problem p5000etch SNF 2010-03-16 18:50:40: Ch. A down
reminder of NEMS seminar today 4pm in allen 101x
shameless self-promotion for the below talk. i hope you can make:
A Start-up's Efforts in DNA Sequencing via Electron Microscopy
J Provine, PhD
Stanford University / Halcyon Molecular
Abstract
There has been significant progress in the past decade to improve the speed and accuracy of genomic sequencing. This technological effort is reaching critical mass as many commercial and academic efforts have continued to increase the pace of innovation. The goal for all those concerned is how to get a complete read of every single base in a genome for low cost (ie < $1000) and at high speed (ie less than 1 hour). In this talk, I will introduce some of the major challenges and players in this effort, discuss our work at Halcyon Molecular and in particular the role of nanostructures and micromachining, and finally give a few short thoughts and lessons learned as a young academic trying to help a start-up.
Biography
J Provine received BA (in Physics), BS (Electrical Engineering), and Masters (also Electrical Engineering) degrees from Rice University in 1998 and 1999. He then received his PhD in Electrical Engineering from Cornell University in 2005 for work on all optical wavelength routers. During his PhD he was able to work at the Berkeley Sensor and Actuator Center where he also was a post-doc for 2005 working on integration of plasmonic filters and MEMS actuators. Since 2006, he has been a research associate at Stanford University working with the Center for Interfacial Engineering in MEMS. In September 2009, he joined Halcyon Molecular part time to aid in their nanofabrication efforts. Before November 2008, you could fit everything he knew about DNA sequencing on this page.
Monday, March 15, 2010
Re: Shutdown p5000etch SNF 2010-03-13 20:48:36: broken wafer
Wafer was broken at the loadlock. Cleaned the chamber and LL. Cycled 32 wafers with no problems.
Ch.B
Cycled 10 wafers.
PhD Oral Examination - SangBum Kim, Tuesday, March 16, 2010: 10:00AM
Special University PhD Oral Examination
Scalability and Reliability Study of Phase-Change Memory
SangBum Kim
Advisor: Professor H.-S. Philip Wong
Department of Electrical Engineering, Stanford University
Tuesday, March 16, 2010, 10:00 – 11:00 AM
Paul Allen Building Auditorium (CISX-101)
(Refreshments served at 9:45 AM)
Abstract
Phase-change memory (PCM) is one of the most mature emerging memory technologies. Superior scalability and reliability are important features that phase-change memory (PCM) technology should demonstrate to expand its usage in various memory applications. In the first part of the talk, scalability study of PCM will be presented. The first principle for PCM scaling rule is studied using analytical analysis. As a PCM cell scales down, the interfacial effect becomes more prominent in material properties and device characteristics due to larger surface area to volume ratio. Various structures have been fabricated to measure these interfacial effects and study its impact on the operation of PCM. In search for a high current-density selection-device with low processing temperature which is needed for integration of PCM in a 3-dimensional 4F2 cross-point array, a Ge nanowire diode has been successfully integrated with a PCM memory cell.
In the second part of the talk, reliability related study is presented. Interaction of thermal program-disturb mechanism and temperature dependence of PCM characteristics poses unique challenges for reliability of PCM devices. To study temperature dependence of PCM characteristics, the micro-thermal stage (MTS) with a fast on-chip heater has been integrated with a PCM cell. The MTS enables experimental study on temperature dependence of crystallization time, drift speed, and threshold switching in microsecond time scale. Thermal disturbance and its impact on PCM operation are measured with the MTS and the relevant model is developed. Based on measurement and modeling results, a new scheme is proposed to improve stability of PCM with a short time annealing pulse.