P5000 Email Log: October 2008

Friday, October 31, 2008

Shutdown p5000etch SNF 2008-10-31 21:33:07: i/o handler error

wafers handler error upon etch completion. Wafers nearly reach casset, but stop slightly short with i/o window open. System will not allow user to go from automatic to manual during the error...otherwise this would be an easy fix. This error has happened the last two times the tool was used (once chamber a, the other chamber b).

Problem p5000etch SNF 2008-10-31 17:37:25: Wafer is stuck inP5000

After the Al etching, my wafer is stuck in the robot arm.

Comment p5000etch SNF 2008-10-31 15:27:35: Ran a few wafers in CH B- ok!

after He valve error fixed.

Re: Problem p5000etch SNF 2008-10-28 15:10:15: wafer chipped in CH B

handling adjusted

Re: Shutdown p5000etch SNF 2008-10-31 09:04:48: Ch.B handling test

Completed test. Cycled 48 wafers with no handling problems.

Comment p5000etch SNF 2008-10-31 14:40:50: Ch.B handling test

Ran 48 wafers through Ch.B with no handling problems.

Shutdown p5000etch SNF 2008-10-31 09:04:48: Ch.B handling test

Cycling many wafers trhough Ch.B

Re: Problem p5000etch SNF 2008-10-30 18:04:34: Wafer Lost/Broken in Chmbr. B

Recovered the user's wafer. Adjusted the wafer placement in the chamber. Cycled 12 wafers with no problems.

Thursday, October 30, 2008

Problem p5000etch SNF 2008-10-30 18:04:34: Wafer Lost/Broken in Chmbr. B

Wafer never returned from chamber B- probably broken. Robot arm had another wafer loaded up, but misplaced on arm. We manually retrieved this wafer. Robot was having a difficult time handling wafers upon retrieval of other wafers- wafers are sticking to robot arm. One wafer was dragged out of cassette and the door shut on the wafer when attempting to retrieve other wafers.

"Cleantamination"

Dear Labmembers --

As you know, the Cleanliness & Contamination working group has its first
meeting last Friday. In the interest of better marketing, we've dubbed
this the "Cleantamination" working group (thanks, J.) The meeting
summary is now posted here:

https://spf.stanford.edu/SNF/processes/cleantamination-group

You may notice that this is a folder on the new labmember wiki. (Beta
testers [and eventually, all SNF labmembers] can add content. For more
info about the wiki, see
http://snf.stanford.edu/cgi-bin/ezmlm-cgi?mss:3452:200810:okgbhkllhlmhjonlggmi)

The next Cleantamination meeting is on Friday, November 7, in CIS 101.
Working groups will update each other. We will try to assess the
available resources for supporting Cleantamination efforts. All
labmembers and PI's are welcome -- but be prepared to take on an
assigned task! (Related, of course, to your process needs.)

You SNF staff

Re: Problem p5000etch SNF 2008-10-30 00:42:21: another wafer stuck in Ch. B

Cleaned chamber B and ran 4 conditioning wafers.

Problem p5000etch SNF 2008-10-30 00:42:21: another wafer stuck in Ch. B

same as last time. helium leak rate error, no wafer came out of chamber. most likely broken like the last one.

missing lab notebook

Dear labmembers,

My lab notebook is lost.

It's a large notebook and has my name Zubin Huang and email huangzb@stanford.edu on it. Would you please email me if you know any information about where the notebook is?

Thank you very much,
Zubin

Wednesday, October 29, 2008

Problem p5000etch SNF 2008-10-29 14:11:56: Ch C RF Power error

Recipe: Ch C POLY ETCH. The recipe gave an RF forward power error and stopped during the main etch step. The set point is 200 W and it dropped to 169.

E342 MEMS Seminar: Bright low-power displays using Digital Micro Shutter(tm) technology. Monday Nov. 3rd, 3-4pm in CISX-101

MEMS Seminar Announcement:
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

E342 SEMINAR
(MEMS Lab2)

Monday, Nov. 3rd, 2008
3:00 – 4:00 pm
CISX-101

Title:
Bright low-power displays using Digital Micro Shutter(tm) technology.

Speaker:
Dr. Lodewyk Steyn
Pixtronix Inc.

Abstract:
Mobile multimedia devices such as smart phones, portable media players and navigation (GPS) devices are playing ever increasing roles in our daily lives. Consumers are no longer just talking and texting, but finding their way, catching the news and watching the latest movies and videos. As we use these devices for more applications and for longer amounts of time, we need larger, brighter, better image quality displays that don't drain the battery dry. Today's LCD technologies struggle to support these requirements. The Pixtronix display technology makes a fundamental breakthrough in the power / performance trade off, delivering 145% NTSC color gamut (CIE 1976), 24-bit color, 1,000:1 contrast ratio and 170° view angles, all at roughly ¼ the power consumption of competing TFT-LCDs. At the heart of this technology is a MEMS-based Digital Micro Shutter™ (DMS™) device that enables the low power, high speed light modulation in the Pixtronix displays. This talk will highlight some of the design innovations in the Pixtronix DMS technology, along with the manufacturing principles that have guided the design process.

Bio.:
Lodewyk Steyn is the Lead MEMS Engineer at Pixtronix Inc. and is responsible for the design and characterization of the proprietary Digital Micro Shutter™ (DMS™) technology of Pixtronix. He was involved with the company since its inception in 2005 and assisted in the due diligence process that resulted in an initial financing round of $9 million. Born in South Africa, he obtained his B.Eng. degree in mechanical engineering from the University of Pretoria. He then relocated to Cambridge, MA to obtain his S.M. and Ph.D. in MEMS at the Massachusetts Institute of Technology. Dr. Steyn likes working with all aspects related to MEMS development, including the design, fabrication and reliability of MEMS devices, as well as the supporting engineering systems and processes required to transform MEMS from a benchtop technology into a product. When he's not designing MEMS devices he can be found mountain biking, snowboarding or kite surfing.

MEMS Packaging Presentation, Monday, 11/3/08, 11 am, CIS 101

WaFER LEVEL Vacuum/Hermetic Packaging of MEMS Devices

The purpose of this talk is to give an overview of MEMS packaging technologies developed at the Wireless Integrated Microsystems (WIMS) center at the University of Michigan. ePack, Inc. is a spin out of the University of Michigan—a short description of this company will be given at the end of the talk. ePack helps companies and researchers implement packaging technologies in order to encourage the commercialization of their MEMS devices.

Two sets of packaging technologies will be discussed. I) Low temperature wafer-level packaging processes for vacuum/hermeticity will be presented including various solder bonding and localized heating technologies. Vacuum pressures lower than 10 mTorr were achieved with yields as high as high as 90% and 3 years of package reliability data. II) A harsh environment robust micromechanical technology (HERMIT) for vibration, shock and thermal isolation as well as vacuum packaging. This technology involves flip chipping MEMS devices onto another wafer which has specially designed vibration/shock/thermal isolation structures where another substrate is then used for batch encapsulation of the devices. This technology was a DARPA funded project was specially developed for high performance gyroscopes, but can be applied to any type of MEMS device.

These technologies are a culmination of several bonding processes, feed-through technologies and various special materials.

Jay Mitchell is president and co-founder of ePack Corp., a company providing packaging services and expertise to companies and researchers in order to bring MEMS devices to market. He finished his doctorate in January of 2008. In the fall of 2002, he began the Ph.D. program at the University of Michigan in mechanical engineering. In his research he developed a Au-Si eutectic wafer-level packaging process and a low temperature localized heating technique for the hermetic/vacuum packaging of MEMS and microsystems. In 2000 and 2001, he worked for Movaz Networks in the testing and design of micromirrors for telecommunications applications. He received his B.S. and M.S. from Case Western Reserve University in 1999 and 2000, respectively. His research interests include: MEMS, micromachining technologies, micromachined sensors, actuators, and micropackaging.

Tuesday, October 28, 2008

Problem p5000etch SNF 2008-10-28 15:10:15: wafer chipped in CH B

Looks like the wafer was slightly missed placed on the chuck so that the clamp finger 'mouse bit' a chunk out of the wafer.

Maskmaking Clinic - Today, 3 pm, CIS 101

Greetings Labmembers --

Bill Martin is here today, ready to answer questions you may have about
maskmaking and layout. It's happening right now, in CIS 101.

Mary

Coral update ....

SNF Lab Members:

I apologize for the fact that it took longer than expected to restore
Coral service following the power shutdown in the computer room ....

The primary problem we encountered is that the flash memory on our
primary file server appears to have somehow scrambled the boot order of
disks and was trying to look in the wrong location. Unfortunately,
because this was the primary file server that provides your home
directories, other systems (such as the Sunrays and the Coral servers)
were left hanging until we resolved this issue.

I believe that all Coral functionality has been resolved at this point
.... and that Web servers, xReporter, and other elements have been restored.

Starting at noon today, I will turn off any hardware interlocks for
tools that have not been enabled in Coral.

Thank you for your continued support and patience,

John

Monday, October 27, 2008

Reminder - University Ph.D. Oral Examination - Alex R. Guichard - Tuesday, 10/28, CISX Auditorium

Growth and Optical Properties of CMOS-compatible Silicon Nanowires

Alex R. Guichard

Department of Materials Science and Engineering

Advisor: Professor Mark L. Brongersma

Tuesday, October 28th, 2008

1:30 PM (Refreshments served at 1:15 PM)

CIS-X Auditorium

Silicon is the dominant semiconductor in both the microelectronics and photovoltaic industries. The main reasons for its success can be traced back to its excellent materials and electronic properties. In contrast, its indirect bandgap makes bulk Si a quite uninteresting optical material. In the early 1990s the discovery of efficient room temperature light emission from electrochemically etched porous Si and subsequent reports of optical gain from Si nanocrystals (Si-nc) early this decade resulted in an explosion of research in this area; these events sparked the dream of realizing Si-based light sources, optoelectronic circuitry, and possibly even a laser. By now, this research has provided a significant understanding of the fundamental optical properties of Si nanostructures. Despite the rapid advancements, an efficient electrically-pumped light source based on these materials does not yet exist. This is in part due to their inefficient charge injection and transport properties. Moreover, the growth processes for Si nanostructures are not yet fully CMOS compatible.

In this presentation, I discuss a potential alternative material system for to porous Si and Si-nc: Si nanowires (SiNWs). I will illustrate the use of CMOS compatible fabrication techniques such as chemical vapor deposition (CVD), lithographic patterning, and thermal oxidation to generate Si NWs with diameters as small as 3 nm. At these diameters, quantum mechanical phenomena substantially modify the electronic and optical properties of the NWs. Photoluminescence (PL) measurements, demonstrate that their emission wavelength can be tuned by precisely controlling the crystalline Si NW diameter, as determined by dark field and high-resolution transmission electron microscopy. The PL decay lifetimes of these NWs are on the order of 50 µs, which suggest the PL is originating from confined excitons in the indirect bandgap Si cores. For solar cell and laser applications, we also quantify undesirable, non-radiative Auger recombination (AR) processes in the NWs. It was found that AR is about 2 orders of magnitude slower than in Si –ncs, which have been a serious contender for a Si-based laser. Although these results are promising, single NW studies reveal the need for better passivation strategies before efficient NW light sources can be realized.

A second potential application for SiNWs is as a building block for low-cost, thin film, Si-based photovoltaics (PV). The market for thin-film PV, particularly organic thin-film PV, exists because it offers a potential cost reduction versus bulk, crystalline-Si-based PV. However, many thin film technologies, while possessing superior optical absorption properties compared to crystalline Si (c-Si), suffer from poor electronic transport properties. Here, I present a new hybrid organic/inorganic PV design that combines the excellent optical properties of highly absorptive organic dye molecules and the useful electronic properties of high-mobility crystalline SiNWs. In the proposed cell, light is first absorbed in the dye and via Förster energy transfer electron-hole pairs are generated in the SiNW. The charges can be extracted from the Si NWs by generating a p-n junction in the wires and contacts at both ends. Here, I investigate the feasibility of such a device by performing photocurrent spectroscopy on individual dye-coated, lightly-doped Si NWs. An approximately twofold increase in the photocurrent is obtained in the wavelength range corresponding to the dye's absorption band, indeed suggesting the possibility to use dyes to boost the efficiency of weakly absorbing Si structures. These results could pave the way for new low-cost, Si-based solar cell designs that leverage the strengths of the Si PV and microelectronics industries.

New SNF website: Call for Beta testers!

Greetings labmembers --

As you may have heard, many students and staff have been working on a
new website for the lab. This is a wiki-based site, designed to be used
by labmembers as a repository for all that info you might need on a
day-to-day basis in the lab. This includes updated operating
procedures, links, recipes, and a few original articles. Our goal is to
gradually shift links from the current website to this one and
eventually move over some time early next year.

We are inviting Beta testers to check out the website, with privileges
to contribute and update content.

If you are interested in being a Beta tester, please get in touch with me --

Mary

Maskmaking Clinic, Tuesday, 10/28, 3 pm

Hi all --

Bill Martin, representing Compugraphics, will be available to answer
questions about maskmaking layouts and how to submit designs for
fabrication. This will be on Tuesday, Oct. 28, at 3 pm in CIS 101.
Bring your layouts and your maskmaking questions to the expert.

Your SNF staff

Notice of Equipment Reservations for Video Shoot

Dear Labmembers,

We would like to inform you that we will be filming a short video for an NSF project on the following equipment and dates/times. The SNF staff has given us their support and approval for the video shoot.

While we have already made the corresponding reservations (with the help of SNF staff) and do not expect any equipment conflicts, we ask that you do not run any wafers on the specified equipment during the listed times and please ensure that your wafers are done and removed prior to the listed times. During the listed times, you will have no/limited access to the equipment (to access your wafers) while we are filming.

We apologize for any inconvenience and we appreciate your understanding.

Thank you very much.

Albert Lin
mrlin@stanford.edu

Equipment Reserved Date/Time
SVG Coater Tracks 1 & 2: 10/29 5pm-6pm
ASML Stepper: 10/29 6pm-7pm
SVG Developer Tracks 1 & 2: 10/29 6:30pm-7:30pm
WBSolvent: 10/30 4:30pm-5pm

Saturday, October 25, 2008

Re: Problem p5000etch SNF 2008-10-23 20:32:56: blade missplaced the wafer in cassette

Adjusted cassette slot spacing..

Friday, October 24, 2008

Re: Comment p5000etch SNF 2008-10-23 14:26:42: Ch.B is down

Adjusted wafer hand-off.

Reminder: Labmembers' Mtg and Cleanliness/Contamination Working Group Mtg today

Hi all --

Just a reminder of the lab-wide, general Labmembers' meeting today, at 1
pm in the CISX Auditorium
http://snf.stanford.edu/cgi-bin/ezmlm-cgi?mss:3437:200810:hjpgkgilegmpbbpjfhie

and the Cleanliness & Contamination Working Group meeting today, at 3 pm
in CIS 101.
http://snf.stanford.edu/cgi-bin/ezmlm-cgi?mss:3438:200810:nooibngkagipcfimmggk

Your SNF staff

SNF Coral and WebSite outage next Tuesday morning ...

SNF Labmembers:

Next Tuesday morning, October 28, from about 8 a.m. to 10 a.m. the power
to the CIS 220 computer room will be taken down to install some
additional electrical service for a computer array. During this time,
the Coral servers, the machine that serves the Sunrays in the lab, the
SNF web site, xReporter, and the Plone web site will be unavailable.

Prior to that time, we will issue the "All On" command to turn on all
interlock on so that work in the lab will not be delayed. As soon as
power is restored and Coral returns to service, we will ask each of you
to disable any tools that you are using .... and will then disable
everything else.

We hope that this will provide a minimal disruption to our activities.

Please contact me if you have any questions and concerns.

Thanks,

John

p.s. PCs and laptops in offices and networking outside of the computer
room should not be affected.

Thursday, October 23, 2008

Problem p5000etch SNF 2008-10-23 20:32:56: blade missplaced the wafer in cassette

blade didn't put the wafer in the cassette perfectly and the warning alarm appeared.

Comment p5000etch SNF 2008-10-23 14:26:42: Ch.B is down

Ch. B is down for wafer handling. Wafer shifts in the paddle during the unload. Need to troubleshoot.

Re: Problem p5000etch SNF 2008-10-23 13:06:36: wafer stuck in Ch. B

Removed broken wafer from the chamber and cleaned the elerode. Replaced burnt lip seal. Ran 4 wafers, He leak rates were all less than 1 sccm. Had problem with wafer shifting in the paddle during the unload.
Chamber is still down.

Problem p5000etch SNF 2008-10-23 13:06:36: wafer stuck in Ch. B

got helium leak rate alarm; ended current step; after the 2 minute cooldown, wafer didn't come out on robot arm to be moved back to cassette. still stuck in chamber B.

PQuest User Survey

Dear PQuest user (or prospective PQuest user):

The Etch Quality Circle is proposing changes to the way the allocation
of etch chemistries is managed at the Pquest. Your inputs would be
greatly appreciated; please see the Survey Monkey link below. The next
Etch Quality Circle meeting is Wednesday, Oct. 29, at 2 pm in CIS 201.
We trust we will have enough input to make the final decision by then.
Interested parties are welcome to attend this meeting (please let us
know if you plan to come.)

http://www.surveymonkey.com/s.aspx?sm=AOqZY6TBzAHBptgBO2szEw_3d_3d

Thanks,

The Etch Quality Circle (tdo, jimkruger, nharjee, jprovine, lwchang,
krivoire, faraon, latta, emyers, shott, eenriquez, mdickey, mtang)

Raman spectroscopy available?

Dear Labmembers,

I am wondering whether I have an access to do Raman spectroscopy on campus or off campus.
I would like to look at Si SOI wafers using this method.
If you have expereicne to share with me, that will be great.

Thanks,
Na Young

Wednesday, October 22, 2008

E342 MEMS Seminar: Monday Oct. 27th 3-4pm in CISX-101; Stress Engineered MEMS: Packaging springs, RF coils and more

MEMS Seminar Announcement:
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

E342 SEMINAR
(MEMS Lab2)

Monday, October 27th, 2008
3:00 – 4:00 pm
CISX-101

Title:
Stress Engineered MEMS: Packaging springs, RF coils and more.

Speaker:
Dr. Eugene M. Chow
Palo Alto Research Center (PARC), California

Abstract:
After a little introduction to PARC, I'll describe how we've been using designed stress gradients (GPa/um) to make a variety of micro-devices. The focus has been on spring based electrical interconnects for electronics packaging. We'll describe various package test vehicles we've built and tested with micrometer scale structures (smaller and more compliant than other approaches). I'll also describe a high Q RF MEMS coil and other work devices we've demonstrated based on this technology.

Bio.:
Eugene M. Chow received a B.S. in engineering physics from University of California, Berkeley (1995), and from Stanford University earned a M.S. in electrical engineering, M.S. in management science and engineering, and a Ph.D. in electrical engineering (2001). At Stanford he worked on silicon micromachining, focusing on through wafer electrical interconnects in silicon, atomic force piezoresistive cantilever arrays, and deep plasma etching. He is currently a research staff member at the Palo Alto Research Center (formerly Xerox PARC), in the Electronic Materials and Devices Lab. There he focuses on MEMS and solid state device research, such as microsprings for integrated circuit packaging, thin film transistors, large area printed organic electronics and novel printing concepts.

MaN adhesion

My experience was that MaN does not like HMDS at all.

A plasma treatment just before spin was much more effective. O2 strip or Ar sputter. Equipment to use depends on if you are "golden" or CMOS clean.

jim

--- On Wed, 10/22/08, James Conway <jwc@snf.stanford.edu> wrote:

> From: James Conway <jwc@snf.stanford.edu>
> Subject: Re: Potential issue with YES oven
> To: "Arash Hazeghi" <ahazeghi@stanford.edu>
> Cc: labmembers@snf.stanford.edu, "Mahnaz Mansourpour" <mahnaz@snf.stanford.edu>
> Date: Wednesday, October 22, 2008, 10:24 AM
> Arash,
>
> You will likely need to perform a more thorough cleaning
> than just
> stripping in acetone as I don't think you are obtaining
> a clean surface
> to prime to.
>
> I would recommend Remover PG heated to between 40 and 60 C.
> with
> ultrasonic for 10 minutes, then a second bath of heated
> Remover PG for
> 5 - 10 minutes with ultrasonic,
> followed by 5 minutes in Acetone (No ultrasonic as it
> appears to often
> break the wafer in the U/S), followed by 5 minutes in
> Isopropanol with
> ultrasonic. Finally a perfect NS blow off and then direct
> into the YES
> Prime Oven.
>
> I used the prime oven yesterday and had normal results.
>
> Best,
>
> James Conway
>
>
> Arash Hazeghi wrote:
> >
> > Hi,
> >
> > I was trying to spin Ma-N 2043 (negative eBeam resist)
> on my wafers
> > (thermal SiO2), I used YES oven but the resist
> adhesion was very poor,
> > literally all the resist came off during spinning
> (like putting water
> > on a hydrophobic surface). The standard Ma-N 2043
> recipe recommends
> > HMDS step and I had successfully coated wafers with
> identical
> > processing in the past with Ma-N 2043. Last night, I
> tried three
> > times, each time striping the wafers in Acetone, and
> putting them in
> > YES oven prior to spinning but it didn't help.
> Nothing has changed in
> > the processing of my wafers so I tend to believe there
> was something
> > in the YES oven last night that caused poor adhesion.
> Has anyone else
> > experienced any similar issues? Is there a solution?
> >
> >
> >
> > Thanks,
> >
> > Arash
> >
> >
> >
> >
> >
> >
> >
> >
> ----------------------------------------------------------------------------------
> >
> > Arash Hazeghi
> >
> >
> >
> > PhD Candidate
> >
> > Stanford Center for Integrated Systems
> >
> > CIS-X 300, 420 Via Palou Mall,
> >
> > Stanford, CA 94305
> >
> >
> >
> > phone: +1-650-725-0418
> >
> > web: http://www.stanford.edu/~ahazeghi
> >
> >
> >

Re: Potential issue with YES oven

Arash,

You will likely need to perform a more thorough cleaning than just stripping in acetone as I don't think you are obtaining a clean surface to prime to.

I would recommend Remover PG heated to between 40 and 60 C. with ultrasonic for 10 minutes, then a second bath of heated Remover PG for 5 - 10 minutes with ultrasonic,
followed by 5 minutes in Acetone (No ultrasonic as it appears to often break the wafer in the U/S), followed by 5 minutes in Isopropanol with ultrasonic. Finally a perfect NS blow off and then direct into the YES Prime Oven.

I used the prime oven yesterday and had normal results.

Best,

James Conway

Arash Hazeghi wrote:

Hi,

I was trying to spin Ma-N 2043 (negative eBeam resist) on my wafers (thermal SiO2), I used YES oven but the resist adhesion was very poor, literally all the resist came off during spinning (like putting water on a hydrophobic surface). The standard Ma-N 2043 recipe recommends HMDS step and I had successfully coated wafers with identical processing in the past with Ma-N 2043. Last night, I tried three times, each time striping the wafers in Acetone, and putting them in YES oven prior to spinning but it didn’t help. Nothing has changed in the processing of my wafers so I tend to believe there was something in the YES oven last night that caused poor adhesion. Has anyone else experienced any similar issues? Is there a solution?

Thanks,

Arash

----------------------------------------------------------------------------------

Arash Hazeghi

PhD Candidate

Stanford Center for Integrated Systems

CIS-X 300, 420 Via Palou Mall,

Stanford, CA 94305

phone: +1-650-725-0418

web: http://www.stanford.edu/~ahazeghi

Re: Comment p5000etch SNF 2008-10-20 10:20:09: Maintenace work

Archived

Re: Comment p5000etch SNF 2008-10-21 07:57:36: NF3 is unavailable

Completed NF3 cylinder change.

Tuesday, October 21, 2008

Comment p5000etch SNF 2008-10-21 07:57:36: NF3 is unavailable

Replacing the NF3 gas cylinder. It should be available by noon.

Re: Problem p5000etch SNF 2008-10-21 01:31:36: WAFER STUCK IN CH A

Recovered the user's wafer and placed in a wafer holder next to the end point monitor.
Cycled 4 wafers using the Ch.A metal recipe with no problems

Adobe Reader on the Sunrays ...

SNF Lab Members:

One of the biggest complaints about the Opteron-based machine used to
support the Sunrays is the absence of Adobe Reader to display PDF
documents. This complaint is widespread among the Solaris x86 community
.... not just here at SNF.

Finally, there is some good news to report on this front:

1. Adobe has finally announced that they will support Adobe Reader on
the Solaris x86 platform on their next major release (Acrobat Reader
9). That is welcome news but, at present, doesn't really help.

2. As an interim measure, Transitive (a company in Los Gatos that
specializes in software that allows applications compiled on Solaris
SPARC architecture to run on other platforms) has recently released
QuickTransit that will allow Adobe Reader to run on the Solaris x86
platform.

I have intalled this program on the flare computer and you should now be
able to fire up this application named "transread" by issuing the command:

transread MyFile.pdf

Note: the full path to transread is /bin/transread.

The first time that you fire up transread, it seems to take a while to
open .... 15-30 seconds ... so be patient. It will first open a licence
agreement and then show you your document.

If you wish to have this open in your browser, once you are in
transread, select "Preferences" from the "Edit" menu. In the
preferences menu, select "Internet". This will open a window that will
allow you to specify the browser to use. In this case, you should enter
the full path to the browser executable:
either /bin/firefox for Firefox users or /usr/sfw/bin/mozilla for
Mozilla users.

Let me know if you encounter any problems .... be we hope that this will
provide you improved access to PDF documents.

Thank you for your continued support,

John

Problem p5000etch SNF 2008-10-21 01:31:36: WAFER STUCK IN CH A

He cooling valve error. didn't want to break wafer so ended current recipe and pressed stop but don't know how to retrieve wafer...please help!

Monday, October 20, 2008

metal delamination during lift-off?

Has anyone ever experienced problems with metallization layers peeling
away during lift-off? I am trying to contact thin (~100 nm) regions
of Si with most of the electrode area in contact with SiO2. Using the
standard lift-off process flow outlined on SNF's website, I have tried
Pd - which supposedly has less than stellar edhesion to SiO2 - and Ni
which has good SiO2 adhesion. Both were deposited with Innotec. In
both attempts, the metals peeled off during the acetone bath step.

Any suggestions would be greatly appreciated.

Thanks!

Alex

University Ph.D. Oral Examination - Alex R. Guichard - Tuesday, 10/28, CISX Auditorium

Growth and Optical Properties of CMOS-compatible Silicon Nanowires

Alex R. Guichard

Department of Materials Science and Engineering

Advisor: Professor Mark L. Brongersma

Tuesday, October 28th, 2008

1:30 PM (Refreshments served at 1:15 PM)

CIS-X Auditorium

OSA/SPIE Seminar: Jon Roth / Aesthera - Thurs. 10/23, 4pm, Ginzton AP 299

The Optical Society of America/SPIE Stanford Student Chapter, and the Stanford Photonics Research Center present:

"Light, Vacuum, Acne: Research at a Medical Device Startup"
Speaker: Jonathan E. Roth, Aesthera

Thursday, October 23, 2008
4:15pm, Ginzton Building, AP 299
Refreshments at 4:00pm

Abstract: Acne is typically treated with drugs. Due to dangers of isotretinoin, a medication used for severe acne, and growing concern over the over-prescription of antibiotics, there is a need for new safe and effective treatments. The first part of this talk will describe a novel acne treatment developed by Aesthera utilizing light and suction. Light is used to selectively heat structures in skin. Suction applied during light pulsing increases the selectivity of absorption by stretching the skin surface while raising the pilosebaceous unit, where acne occurs, towards the surface. Further ongoing research to
improve acne treatment will be discussed.
The second part of the talk will focus on the experience of working in a startup, and contrasts with academia. While long-term research can boost the valuation and chances of long-term success of a small company, the startup must focus on short term profitability to gain solid footing. The product development process for a medical device
will also be discussed.

About our speaker: Jon Roth earned a Ph.D. in 2007, working with optoelectronic modulators in David Miller's group. In 2008 he joined Aesthera, a startup which sells medical devices to dermatologists.

Comment p5000etch SNF 2008-10-20 10:20:09: Maintenace work

Replaced the noisy loadlock pump.

Cleanliness & Contamination Working Group: Meeting this Friday, 3 pm

Labmembers:

Since our meeting on cleanliness and contamination a few weeks ago, many
meetings and discussions have taken place. Again, we'd like to
emphasize that no policy decisions have been made. Instead the
discussions have focused on how to structure an ongoing forum whereby
the lab community can work out how new process flows can be incorporated
into the lab without risking others' work..

The first cleanliness and contamination working group meeting will be
this Friday, Oct. 24, at 3 pm, in CIS 101. The philosophical approach
NOT a radical shift in the basic cleanliness and contamination policies
of the lab, but rather to facilitate pathways to meet more of our
labmembers' processing needs. The discussion at this meeting is
intended to be at a fairly high level, where other working groups and
activities may be spun out to address specific issues in more detail.
Certain PI's may be invited to participate as appropriate. Meeting
minutes will be posted for the lab community.

The objective in this first meeting will be to identify specific process
technologies with special needs and identify the labmember advocate who
will represent this technology in working group meetings. Several
people have already volunteered (or been volunteered by their PI's) to
represent the following areas: novel materials for CMOS; memory; GaAs
on Si; detectors; EE410; MEMS; nanowires, solar. If you have specific
critical needs for your process technology, whether it is to maintain a
certain level of cleanliness or introduce a previously untested
material, and you are willing to serve as an advocate for your process
technology, then we invite you to participate in this working group
meeting.

Thanks for your attention --

Jim McVittie, Ed Myers, Peter Griffin, John Shott, Mike Deal, & Mary Tang

Sunday, October 19, 2008

Labmembers' Meeting, Friday, Oct. 24, 1 pm, CISX Auditorium

Hi all --

Just a reminder of the Labmembers' meeting this Friday, Oct. 24, 1 pm, in the CISX auditorium. On the agenda --

- General announcements
- Quality Circle updates
- Wiki website
- Cleanliness & Contamination Working Group
- EE410 Redesign project
- Other project updates

All this, and more.

Everyone in the lab community is welcome.

Your SNF Staff

Process Clinic, 2-4 pm Monday

Hi all --

The next Process Clinic is Monday, Oct. 20, from 2-4 pm in the cubicle
area near Maureen's office. Bring your process flows, process
questions, layouts, and new material requests. Senior labmembers are
especially welcome to offer first-hand advice and suggestions.

Your SNF staff

Wednesday, October 15, 2008

Re: Problem p5000etch SNF 2008-10-10 14:35:09: ch a particles

After pumping the chamber for 2 hours, leak test was 75 mt/min. After closing and capping the manual vent........ the leak rate was < 1 mT/min.
Particle test wafers (oxide wafers) looked much cleaner.
Rostam ran his device wafer using Ch.A metal recipe and saw NO particles under the microscope.
We will repair the ballast purge valve tomorrow or Friday.

Re: Comment p5000etch SNF 2008-10-13 11:25:03: Ch.A down for particles

Re: Comment p5000etch SNF 2008-10-15 11:26:41: Ch.A particle update

Fine Al or Au bonding wire

Hi all,

I'm trying to find some Al or Au bonding wire, in 0.5 or 0.7 mil diameter. Turns out it's expensive to order, and I don't really need much, so if anyone can loan me a spool that'd be very helpful!

(Or if you know where I might find some, that'd be useful too.)

Thanks much,
Dan.

Comment p5000etch SNF 2008-10-15 11:26:41: Ch.A particle update

Unable to run a chamber leak rate yesterday because the turbo backing pump had a high base pressure. The turbo backing was also leaking through. Also found the pump purge not functioning.
- We changed the pump oil. Now base pressure ~ 50 mT
- We cleaned the tubo isolation valve. Now able to isolate the chamber from the pump.
- Still need to repair the pump purge.
Initial leak up rate was very high at ~ 86 mT/min (should be < 5 mT/min).

Tuesday, October 14, 2008

Comment p5000etch SNF 2008-10-14 22:33:04: Chamber A

I vented the chamber A and did a full wet clean.
Chamber will need to be condition with coated resist
wafers before checking pc.

Bionanoparticle Characterization Workshop, Tuesday, Oct. 21, 2008

Dear Labmembers --

SNL and SNF are holding a workshop on the characterization of
nanoparticles for biology as part of the NCI Alliance program for Cancer
Bionanotechnology. This workshop will be held from 9 am - 3 pm in the
Stanford Nanocharacterization Lab next Tuesday, Oct. 21, 2008. The
morning session (9-11:30) will consist of lectures introducing basic
concepts of bionanoparticle characterization and modification; the
afternoon (12:30-3) will consist of hands-on demos in the
Nanocharacterization Lab.

Registration is free to academic researchers.

Please RSVP to Richard Chin (rwchin@stanford.edu) by Friday, Oct. 17, if
you would like to attend.

Monday, October 13, 2008

Comment p5000etch SNF 2008-10-13 11:25:03: Ch.A down for particles

SiO2/PR selectivity in MRC

Hi,

Does anyone have an MRC recipe for an SiO2 etch that's got at least a 2:1
selectivity over the 955 photoresist (or 3612, if that's all you have)?

Last week, I did an etch with 2.5 sccm O2, 15 sccm CHF3, 50W, 50mT, but
found it etched PR *faster* than SiO2 (I need the opposite). I've had
suggestions of pumping down the chamber longer to remove residual O2,
reducing the O2 flow rate, and breaking the etch into pieces to keep the
sample from heating up.

Thanks in advance,
John

Re: Problem p5000etch SNF 2008-10-12 07:11:59: endpoint PC not working

No problem found. Ran wafers using Ch.B oxide with no problems.

Sunday, October 12, 2008

Problem p5000etch SNF 2008-10-12 07:11:59: endpoint PC not working

not triggered when RF starts.
Note: haven't tried power cycling the PC

Saturday, October 11, 2008

ITO deposition

Dear Labmembers,

We need to deposit ITO (Indium tin oxide) on some wafers. Could anybody provide a good company that can do this?

Thanks!

Xinran

Friday, October 10, 2008

Problem p5000etch SNF 2008-10-10 14:35:09: ch a particles

I did 40sec of CH.A METAL recipe. I could see black junk particles all over the wafer under optical microscope. These particles are interfering w/ my process. Can't continue my process unless this problem is fixed.

Re: Comment p5000etch SNF 2008-09-24 19:03:20: Update Ch.A particles

Will keep an eye on this particle issue

Comment p5000etch SNF 2008-10-10 14:09:25: CH B qual

ER Ox = 3508A/min
ER PR = 2145A/min
Sel Ox:PR = 1.6:1
Used CH B OXIDE program.

Re: Comment p5000etch SNF 2008-09-23 14:24:20: CH B qual after shower head clean

newer qual posted.

Re: Problem p5000etch SNF 2008-09-24 10:29:43: ch. A still leaves particles on wafer

We ran three wafers (one bare Si, one 1000A themal ox and one 3612 on bare Si) for 60 secs using CH A MEATAL. We then ran them through the surfscan. First off, the oxide wafer overloaded the tool. We think this may be due to surface roughness- the etch did not completely remove the oxide.
But the other two showed very few particles. Most are in the 2-10um range. The blank wafer was the worst with 1185. A control wafer showed 37.
So some particles may be generated during the etch, but not nearly to the degree we observed a couple of weeks ago.

Re: Comment p5000etch SNF 2008-09-23 14:18:48: test run after CH A clean-up

to archives

Re: Problem p5000etch SNF 2008-09-24 14:28:52: CH A down for major clean

cleaned and back up

Re: Problem p5000etch SNF 2008-10-09 19:07:09: helium leak is too high

Talked to user. He was able to resume etching....

Problem p5000etch SNF 2008-10-10 12:18:36: disk full error will not clear.

Tool runs fine, though.

Thursday, October 9, 2008

Problem p5000etch SNF 2008-10-09 19:07:09: helium leak is too high

The helium leak was high during the break through and process stopped.

E342 MEMS Seminar; Zero to Millions: High Volume MEMS Start-Ups in the Fabless Era, Monday Oct. 13th, 3-4pm CISX 101

MEMS Seminar Announcement:
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

E342 SEMINAR
(MEMS Lab2)

Monday, October 13, 2008
3:00 – 4:00 pm
CISX-101

Title:
Zero to Millions: High Volume MEMS Start-Ups in the Fabless Era

Speaker:
Dr. Brian Bircumshaw
LV Sensors, Inc., Emeryville, California

Abstract:
So, you have a novel MEMS widget and you want to start a company? The reality of today is that credit is tight. Technology speculators (like venture capitalists) increasingly back "safer" software options. They will not fund a fab; and, to succeed, you will need a system with market pull, not a widget. Despite these limitations, MEMS is entering the mainstream, and there are many opportunities out there. This talk will delve into the topic of building a high volume MEMS start-up in the fabless/fab-lite era. It will explore the necessary conditions for success on the business side. It will then examine the constraints imposed by the investors and the marketplace. With the business landscape established, the talk will delve into system design considerations, from the MEMS to the package & electronics, from wafer probe to product test and calibration. The talk will also touch on the extremely important topic of sub-contractors, such as wafer foundries.Throughout, the talk will draw on examples and vignettes from LV Sensors, Inc. (LVSI). Once described as a "secretive wireless sensor co.," LVSI is an example of a high volume electronics start-up. Combining MEMS and electronics in a custom package, LVSI has developed the world's first Tire Pressure Sensor (TPS) with integrated pressure sensor, RF capabilities, and dual-axis motion sensor.

Bio:
Brian Bircumshaw was born and raised in San Diego. He received his BS with Honor from Caltech in Mechanical Engineering. His passion for traveling motivated him to look abroad for his post-graduate degrees. In 1999, he received his MPhil from Cambridge University ( England ) in computational fluid dynamics on a Churchill Fellowship. In 2000, he received a diploma in technology management from the University of Strathclyde ( Scotland ) on a Rotary Ambassadorial Scholarship. Excited by ants on microscopic gears, Brian returned to the USA to work on MEMS at UC Berkeley with Profs. Al Pisano and Roger Howe. In 2005, he received his PhD in RF MEMS resonators, and began working at LV Sensors with the start-up personalities of Dr. Janusz Bryzek and Curtis Ray. Brian is the principal architect behind the design of LVSI's MEMS pressure sensor and accelerometer, as well as their fabrication process flow and integration into the TPS product.

Wednesday, October 8, 2008

Comment p5000etch SNF 2008-10-08 17:33:55: CH C Qual result after clamp replaced and RF cal'd

Ran two wafers-
Si etch rate = 2260A/min and 2270A/min
PR = 460A/min and 590A/min- used SPR220-3 and -7. PR etch rate for 3612 should be a bit less.

Re: Problem p5000etch SNF 2008-10-03 11:39:46: CH C did not pass qual

Quals run again and are consistant with April 08 quals

Re: Comment p5000etch SNF 2008-10-08 10:20:39: Update Ch.C etch rate

Qual done. Good enough to relase CH C.

Re: Comment p5000etch SNF 2008-09-22 11:35:10: Update Ch.B uniformity

Archived

Postdoctoral Opportunity at the University of Maryland

Student OSA/SPIE and labmembers,

Please see below for a postdoc opening from Edo Waks, a former Stanford Ph.D student and postdoc.

Postdoctoral Fellow Opening

Department of Electrical and Computer Engineering

University of Maryland, College Park

The nanophotonics group at the University of Maryland, College Park, is seeking to hire a Postdoctoral Fellow. The main interests for our research group are: experimental and theoretical quantum optics, quantum information processing, photonic crystal design and fabrication, quantum dots, physics of optoelectronic devices, and plasmonics. We are particularly interested in candidates with optics lab and nanofabrication experience.

The nanophotonics group is led by Edo Waks, and is part of the Department of Electrical and Computer Engineering. Our group is part of the newly formed Joint Quantum Institute (JQI), as well as the Inistute for Research in Electronics and Applied Physics (IREAP). JQI brings together leading researchers from both NIST and Maryland to study quantum coherence and quantum information, while IREAP combines the expertise of top scientists from Departments of Physics, Electrical Engineering, and Material Science to perform highly multidisciplinary research. Postdocs will have the opportunity to establish close ties with researchers at Maryland, NIST, and IREAP. They will also have access to state-of-the-art nanofabrication facilities at the University of Maryland Fablab and NIST.

The initial appointment will be for one year with the possibility of renewal for an additional one to two years subject to satisfactory progress and availability of funds. The start time of the appointment is open to negotiation. Qualified candidates must have attained a Ph.D. prior to the beginning of their appointment. Applicants should send a detailed CV along with 3-4 references by email to edowaks@umd.edu. Please make the header of your email is "Nanophotonics Research Position" to ensure that it is appropriately received. Additional information may be found on our web page at http://www.ireap.umd.edu/NanoPhotonics/. Email applications are preferred, but if a hard copy application is required it may be mailed to the following address:

Edo Waks

Institute for Research in Electronics and Applied Physics

University of Maryland

College Park, MD 20742-3511

--
--------------------------------------------------
Meredith M. Lee
Stanford University
Ph.D. Candidate, Dept. of Electrical Engineering
President, Stanford Student OSA/SPIE

Center for Integrated Systems
420 Via Ortega, Stanford, CA 94305-4075
Fax: (650) 723-4659
mmlee@stanford.edu

Comment p5000etch SNF 2008-10-08 10:20:39: Update Ch.C etch rate

Calibrated the RF generator @ 0 -400 Watt range. Need to run process qual.

Tuesday, October 7, 2008

Re: Problem p5000etch SNF 2008-10-02 23:00:49: blade drags wafer back with it

Comment p5000etch SNF 2008-10-07 20:02:38: Wafer transfer

Adjusted wafer handoff from cassette elevator to storage
elevator and checked wafer transfer on both a and b
cassette.

Re: Problem p5000etch SNF 2008-09-23 14:29:51: CH C down

Clamp installed.

Re: Comment p5000etch SNF 2008-10-03 14:53:17: Ch.C is still down

After the chamber door speed adjustement, cycled 80 wafers through Ch.C without any problems.

Re: Comment p5000etch SNF 2008-10-06 14:46:02: Update Ch.C

After the chamber door speed adjustement, cycled 80 wafers through Ch.C without any problems.

Veeco AFM seminar Reminder

>All,
>
>Mayur Savla the Veeco Bay Area AFM Applications Engineer, will hold
>a seminar on:
>
>Wednesday, October 8 at 2:30 to 3:15 PM
>Allen Center for Integrated Systems
>CIS-X Cypress Auditorium (CISX101).
>
>He will discuss the best practices and set-up tips for optimizing
>scan parameters for surface roughness and step height measurements,
>Force curve measurements, Phase imaging, Fluid imaging and
>Electrical Measurements using AFM.
>
>Registration is required if you want to win the free sample pack of
>AFM tips. See the flyer for instructions.
>
>If you have any questions, please feel free to contact me or Paul
>Charell at <mailto:pcharell@veeco.com>pcharell@veeco.com.
>
>Regards,
>Ed

Extended Deadline for Papers/Abstracts: October 21, CSIE 2009, Los Angeles

(We are pleased to announce Keynote Speakers: Bir Bhanu, IEEE Fellow;
Lixia Zhang, IEEE & ACM Fellow)
(Due to many requests, the submission deadline is now extended
to October 21, 2008)

2009 World Congress on Computer Science and Information Engineering
(CSIE 2009)

March 31 - April 2, 2009
Los Angeles/Anaheim, USA

http://world-research-institutes.org/conferences/CSIE/2009

CALL FOR PAPERS/ABSTRACTS, INVITED SESSIONS & EXPO

The Los Angeles/Anaheim area is known for its many renowned
attractions, such as Disneyland, Universal Studios and the
Hollywood Walk of Fame. Very few cities in the world offer
as much entertainment, excitement and diversity as Los
Angeles/Anaheim does.

CSIE 2009 conference proceedings will be published by the IEEE
Computer Society and all papers in the proceedings will be
included in EI Compendex, ISTP, and IEEE Xplore.

CSIE 2009 intends to be a global forum for researchers and
engineers to present and discuss recent advances and new
techniques in computer science and information engineering.
CSIE 2009 consists of the following Technical Symposiums:

* Computer Applications Symposium
* Communications & Mobile Computing Symposium
* Computer Design & VLSI Symposium
* Data Mining & Data Engineering Symposium
* Intelligent Systems Symposium
* Multimedia & Signal Processing Symposium
* Software Engineering Symposium

Invited sessions offer focused discussions on specialized topics.
A prospective invited session organizer should send a proposal,
including a session title, a short synopsis, bio-sketch of the
organizer with a publication list, to the appropriate Symposium
Chair (visit the conference website for more details).

In addition to research papers, CSIE 2009 also seeks exhibitions
of modern products and equipment for computer science and
information engineering.

Keynote Speakers:

Bir Bhanu, IEEE Fellow, University of California at Riverside
Lixia Zhang, ACM & IEEE Fellow, University of California at Los Angeles

Important Dates (Extended):

Paper/Abstract Submission Deadline: October 21, 2008
Review Notification: December 7, 2008
Final Papers and Author Registration Deadline: January 7, 2009

Organizing Committee:

General Chair:
Adrian Martin, World Research Institutes, USA

Program Chair:
Mark Burgin, University of California at Los Angeles, USA

Symposium Chairs:
Masud H Chowdhury, University of Illinois at Chicago, USA
Chan H. Ham, University of Central Florida, USA
Simone Ludwig, University of Saskatchewan, Canada
Weilian Su, Naval Postgraduate School, USA
Sumanth Yenduri, University of Southern Mississippi, USA

Publicity Chair:
Nitin Upadhyay, Birla Institute of Technology and Science
(BITS), India
David C. Wong, US Environmental Protection Agency, USA

(Please forward to those who may be interested.)

(To unsubscribe all WRI announcements, please reply with the
email subject being "Unsubscribe ALL p5000etch-pcs@snf.stanford.edu".
Thanks and apologies)

(To unsubscribe CSIE announcements only, please reply with the
email subject being "Unsubscribe CSIE p5000etch-pcs@snf.stanford.edu".)

Monday, October 6, 2008

Re: Reminder: Cleanliness & Contamination Meeting, Thursday, 9/25, 3 pm

Following last meeting, we were told "nothing had been decided yet."

After all the opposition and questions at that meeting, I'm hoping
that there is a followup discussion for such a dramatic shift in
the mission of the lab. Is anything scheduled or planned?

Thanks,
-Eric

On Thu, 25 Sep 2008, Mary Tang wrote:

> Hi all --
>
> Just a reminder. For details:
>
> http://snf.stanford.edu/cgi-bin/ezmlm-cgi?mss:3413:200809:phkllicgjinehokifeok
>
> Your SNF Staff
>
> --
> Mary X. Tang, Ph.D.
> Stanford Nanofabrication Facility
> CIS Room 136, Mail Code 4070
> Stanford, CA 94305
> (650)723-9980
> mtang@stanford.edu
> http://snf.stanford.edu
>
>

Seminar Today: Retro-Mechanical Era? From MEMS to NEMS switches, 3-4:30pm CISX 101]

E342 SEMINAR
(MEMS Lab2)

Monday, October 6, 2008
3:00 - 4:30 pm
CISX-101

Title:
Retro-Mechanical Era?
From MEMS to NEMS switches

Speaker:
Prof. Jun-Bo Yoon
KAIST University, Korea

Abstract:
A switch has been playing very important role on our human history.
For example, manual phone line switching gave us a great motivation to
invent a transistor at Bell lab in around 1950. After dramatic
progress in the modern integrated circuit technology, we now are
sitting on a position looking back our mechanical switch era. Why? I'd
like to discuss the reason with you while presenting recent progresses
achieved in MEMS and NEMS switches in this talk.

Re: Shutdown p5000etch SNF 2008-10-06 08:54:21: Working on Ch.C

Found the LL door bounced several times as it opens. Adjusted the LL door opening speed. Cycled 10 wafers with no problems. Will test again tomorrow.

Comment p5000etch SNF 2008-10-06 14:46:02: Update Ch.C

Found the LL door bounced several times as it opens. Adjusted the LL door opening speed. Cycled 10 wafers with no problems. Will test again tomorrow.

Shutdown p5000etch SNF 2008-10-06 08:54:21: Working on Ch.C

Venture Clinic w/Shahin Farschi, Tues. 10/7, 3 pm

Are you thinking about the possibility of building a startup?

Shahin Farshchi, an Associate from Lux Capital, will be moderating the Venture Clinic,
which aims to provide an informal forum for researchers interested in brainstorming
with a venture capitalist on avenues for commercializing technology, and what to expect
when starting a new venture.

Technical discussions should be limited to what has been already disclosed or published.

This will take place on Tuesday, Oct. 7 at 3 pm in CIS 101.

For more information, contact:

Shahin Farshchi, Ph.D.
Phone: 925.323.2784
Email: shahin.farshchi@luxcapital.com

<http://snf.stanford.edu>

--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu

Sunday, October 5, 2008

SNF Process Clinic, Monday, 10/6, 2-4 pm

Hi all --

Next Process Clinic is Monday, 10/6 from 2-4 pm in the cubicle area near
Maureen's office. Bring your process questions, your process flows,
device layouts, and new materials requests. Keith Best from ASML
will also be on hand. All labmembers (and prospective labmembers)
are welcome.

Your SNF Staff

Friday, October 3, 2008

Comment p5000etch SNF 2008-10-03 14:53:17: Ch.C is still down

Intermittent robot extension problem.

Re: Shutdown p5000etch SNF 2008-10-03 11:48:01: robot extention error

Rehomed the robot and recovered the wafer. Placed all 4 wafers in the user's cassette.

Shutdown p5000etch SNF 2008-10-03 11:48:01: robot extention error

after putting wafer into CH C.

Problem p5000etch SNF 2008-10-03 11:39:46: CH C did not pass qual

PR etch rate = 458A/min (ok)
Si etch rate = 2217A/min (about half of expected)
Surface is spotty.
Used CH C POLY ETCH
I'll run some Si and PR wafers through to further condition

Wednesday, October 1, 2008

Si wet etching

Does anybody know how to wet etch Si? What kind of etchant can I use?
what's the etching rate?
Thank you very much!

Jeff Sun

Friday, October 31, 2008

Thursday, October 30, 2008

Wednesday, October 29, 2008

Tuesday, October 28, 2008

Monday, October 27, 2008

Saturday, October 25, 2008

Friday, October 24, 2008

Thursday, October 23, 2008

Wednesday, October 22, 2008

Tuesday, October 21, 2008

Monday, October 20, 2008

Sunday, October 19, 2008

Wednesday, October 15, 2008

Tuesday, October 14, 2008

Monday, October 13, 2008

Sunday, October 12, 2008

Saturday, October 11, 2008

Friday, October 10, 2008

Thursday, October 9, 2008

Wednesday, October 8, 2008

Tuesday, October 7, 2008

Monday, October 6, 2008

Sunday, October 5, 2008

Friday, October 3, 2008

Thursday, October 2, 2008

Wednesday, October 1, 2008

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