Has anybody etched Ti in drytek1 or 4? In Wiki, it says drytek1 or 4 can be used for Ti etching. But it doesn't specify about gas and etch rate. My samples are gold contaminated so I can't use p5000. If there are any tool for Au contaminated Ti etching rather than drytek, please let me know. Thank you in advance.
Kyunghoae
Mahnaz Mansourpour wrote:
>
> Hello all,
>
> I am happy to announce that there will be a presentation given on
> spray coater by Chad Brubaker, the head of process technology, from
> EVG.
>
> *on
> Wednesday in Allen 101 ( CIS 101) at 1 pm.*
>
> There will be time at the end of session for discussions and questions.
>
>
> cheers
> mahnaz
I am happy to announce that there will be a presentation given on spray
coater by Chad Brubaker, the head of process technology, from EVG.
*on
Wednesday in Allen 101 ( CIS 101) at 1 pm.*
There will be time at the end of session for discussions and questions.
cheers
mahnaz
Title: 'Materials for UV-assisted Nanoimprint Lithography Ready for Industrial Use' Presented by: Dr. Freimut Reuther Technical Director micro resist technology GmbH Koepenicker Str. 325 GERMANY Phone: +49 30 6576 2192 Email: f.reuther@microresist.de Internet: www.microresist.com
SUPR 2010 is here!
We've got an amazing line up of speakers and an exciting weekend planned
[ Register now – Space is limited! ]
It's my pleasure to announce that John Shott is the Director of the SNF,
having been in that role since last September. The position was
approved formally only a couple of days ago. Needless to say, the lab
is in great hands -- I'm looking forward to working with him on the many
opportunities and challenges facing us in the next few years.
Roger Howe
Faculty Director
I believe all the process gases are back on line and the facility
is fully functional. As with any event (or good engineering
practice), monitor your process to make sure the systems are running.
What happened today was a real event in a lab in the CISX
building. During a major, biannual cleaning there was a flair up of
the deposited material when it was exposed to the atmosphere. The
flair up was small and short lived, but it produced enough smoke to
trigger the smoke alarm in the room causing the building to be
evacuated. Any time there is a smoke alarm the fire department is
called in and they take responsibility for the subsequent chain of
events. Today's evacuation was more lengthily, with many more
departments responding because of health concerns raised by some of
the materials used in the system. The fire department needed to make
sure the room and building would be safe for our reentry. Thankfully
no one was injured and ultimately the building was deemed safe.
Regards,
The SNF Staff
on behalf of the Palo Alto Fire Department, Stanford Police
Department, Stanford EH&S to name a few.
Pushkar Apte
Vice President, Technology
Semiconductor Industry Association
Host: Prof. Krishna Saraswat
Tuesday, March 2, 2010
4:15 - 5:05 pm
Hewlett 102
Unprecedented global shifts in markets and technology are creating an inflection point for the semiconductor chip-driven high-tech ecosystem. Corporations in the developed economies were the leading users of high-tech products for a few decades, but the market has shifted rapidly over the last few years to the consumer and to emerging economies. These segments have a different set of needs and diverging perceptions of value, which makes the development of new products and solutions challenging. In parallel, we are reaching the limits of progression of the current workhorse technology. This has led to an escalation, at a never-before pace, in the cost for developing new products and in the number of technology options. This is true for each element of the supply-chain, including design, process technology, manufacturing, packaging, software and systems. These challenges are accentuated further by the global economic downturn. Challenge also brings opportunity, and future growth has many exciting drivers – including nanotechnologies, new applications like energy and healthcare, and an increasing customer base in emerging economies. However, a fresh approach is needed to support the new vectors of research and innovation, together with creative networking and collaboration models to minimize cost. In this paper, we present a "big-picture view" of the causes and development of this high-tech inflection, and outline possible actions for industry, academia and government to realize the opportunity created.
Biography: Dr. Pushkar Apte is vice-president of Technology Programs, for the Semiconductor Industry Association. As such he has oversight responsibility for all of the technology activities of the SIA. This includes the SIA's International Technology Roadmap for Semiconductors. It also includes the collaborative efforts of the manufacturing and research consortia, (SEMATECH, SRC) set up by the SIA in the 1980s, and the Focus Center program set up by the SIA in 1998. His experience includes five years at Texas Instruments Incorporated, where he worked on cutting-edge research and technology development, and five years with McKinsey & Company, as their global semiconductor expert. He received his M.S. and Ph.D. degrees from Stanford University in Materials Science and Electrical Engineering, and his B.S. degree from the Indian Institute of Technology, Varanasi, India.
Title: 'Materials for UV-assisted Nanoimprint Lithography Ready for Industrial Use' Presented by: Dr. Freimut Reuther Technical Director micro resist technology GmbH Koepenicker Str. 325 GERMANY Phone: +49 30 6576 2192 Email: f.reuther@microresist.de Internet: www.microresist.com
>Xactix, the manufacture of our XeF2 etch system will be on campus
>Wed. Feb. 24th. If you have any interest in the latest developments
>in XeF2 etching please join us.
>
>Latest Research Results and Applications using XeF2 etching.
>David Springer and Kyle Lebouitz, XACTIX, Inc.
>Wednesday February 24, 10:00am to 12 noon:
>Room: CIS101
>
>This seminar will be divided into two parts. The first hour will be a
>presentation by David Springer, President of XACTIX, Inc. on the latest
>research results and examples of etching using XeF2 gas for multiple
>applications. In the second hour we will be joined by Kyle Lebouitz, XACTIX's
>CTO, for users to have a chance to discuss particular ideas, issues, problems
>with their use of the XACTIX XeF2 etcher in the fab.
>
>XeF2 etches Si, Ge, Mo and SiGe very selectively to most semiconductor
>materials. For example selectivities of over 1000:1 can be archived to films
>such as SiO2, and SiN with zero attack on almost all other materials
>including
>Al, PZT, AlN, photoresist, etc. XeF2 can also be used to etch transitional
>metals such as W, Ti, Ta, TiN and TaN, or conditions can be set to preserve
>these materials when etching silicon. Areas where XeF2 etching can
>show benefit
>include releasing MEMS, increasing die strength after dicing,
>removing barmier
>layers for metal deposition, removing silicon for failure analysis, removing
>silicon to expose the back of side of sensor circuits to enhance signal
>strength as well as other non semiconductor applications which
>require removing
>transitional metals.
>
>
>If you have any questions, please contact Ed Myers
Just a reminder that there is a Process Clinic today (Monday) from 2-4
pm in the cubicle area outside of Maureen's office. Staff and senior
labmembers will be on hand to answer questions and brainstorm ideas to
address process issues. Bring your ideas, process questions, your
process runsheets, device layouts, and whatever else.
Your SNF staff
--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu
Lan Wei
Advisor: H.-S. Philip wong
Time: 10am (Refreshment at 9:45am)
Date: Feb 22 (Mon), 2010
Location: Paul Allen Building Auditorium (CIS-X Aud)
Nanoelectronics: Technology Assessment and Projection at the Device, Circuit, and System Level
Abstract:
Nowadays, physical gate length can no longer be effectively scaled down and traditional boosters (e.g., strain, high-k/metal gate) are exhibiting diminishing returns on performance improvement. Continued progress in nanoelectronics necessitates a holistic view across the boundaries of device, circuit and system domains. The best devices are those that are optimized for the circuits and systems of the target application. Device design and engineering must aim at improvements at the circuit and system levels. At the same time, new applications in various areas, such as life-science, are enabled by emerging technology.
In this talk, the design space is explored for future Si CMOS technology and for carbon nanotube field effect transistors, a promising technology in the post-Si era. Compact models for transport properties and capacitive components of different device structures have been developed to facilitate circuit-level analysis and system-level optimization. Possible ways of extending the technology roadmap are proposed. We propose scenarios of selective device structure scaling that will enable Si CMOS technology scaling for several generations beyond the currently perceived limits. Beyond Si CMOS scaling, carbon nanotube field effect transistors (CNFETs) are optimized and projected to achieve 5x chip-level speed up over PDSOI at 11 nm technology node for a high-performance four-core processor with 1.5M logic gates and 5MB SRAM per core.
There was a momentary power glitch around 11 am. It looks like only the
furnaces were affected; Maurice, Ted, and Ray are working on them now.
However, it is possible that we may have overlooked something. Please
exercise a little more attention when using equipment today and report
any issues on Coral.
Thanks,
Your SNF Staff
--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu
Does anyone have an experience with using silane coupling agents (e.g. OTS or APTMS or else) to render a surface hydrophobic?
Thank you,
Pascale El-Kallassi
Postdoctoral Associate,
Stanford University Electrical Engineering Dpt
330 Serra Mall, Paul G. Allen building X
Palo Alto, CA 94305-4075
office (650)725-6970
fax (650)723-4659
e-mail: elkallas@stanford.edu
-
Latest Research Results and Applications using XeF2 etching.
David Springer and Kyle Lebouitz, XACTIX, Inc.
Wednesday February 24, 10:00am to 12 noon:
Room: CIS101
This seminar will be divided into two parts. The first hour will be a
presentation by David Springer, President of XACTIX, Inc. on the latest
research results and examples of etching using XeF2 gas for multiple
applications. In the second hour we will be joined by Kyle Lebouitz, XACTIX's
CTO, for users to have a chance to discuss particular ideas, issues, problems
with their use of the XACTIX XeF2 etcher in the fab.
XeF2 etches Si, Ge, Mo and SiGe very selectively to most semiconductor
materials. For example selectivities of over 1000:1 can be archived to films
such as SiO2, and SiN with zero attack on almost all other materials
including
Al, PZT, AlN, photoresist, etc. XeF2 can also be used to etch transitional
metals such as W, Ti, Ta, TiN and TaN, or conditions can be set to preserve
these materials when etching silicon. Areas where XeF2 etching can
show benefit
include releasing MEMS, increasing die strength after dicing, removing barmier
layers for metal deposition, removing silicon for failure analysis, removing
silicon to expose the back of side of sensor circuits to enhance signal
strength as well as other non semiconductor applications which
require removing
transitional metals.
If you have any questions, please contact Ed Myers
As of now the lab is back to normal with respect to temperature and
humidity. At SNF's request, the Steam shop worked to restart systems
early. With regard to the ASML, Mark, the service engineer, will be in
later this morning to check the system so please do not use until he has
done so.
Many thanks for your patience and apologies for the inconvenience.
Your SNF staff
Bill Martin will be on hand Tuesday, Feb. 16, at 3 pm, to answer
questions about maskmaking and mask layouts. Bill has many years of
experience in making masks for industry and research and now represents
Compugraphics and other suppliers specializing in University accounts.
Bring your maskmaking questions and bring your CAD files to show Bill.
We will meet in the cubicle area outside Maureen's office.
Your SNF Staff
We have learned that there will be another shutdown to the steam system
that heats this building to complete the tie-in to the new Nano Center.
They will plan to shutdown the system starting this Friday, February 12
at 10 p.m. They expect to have service restored by early Monday
morning, February 15 ... and may get things back up late in the day on
Sunday, February 14.
We have met with both the Superintendent of the Nano Center construction
team and with the head of the Stanford Steam Shop. They understand how
critical temperature control is to our operation and have assured us
that they will do everything possible to minimize the downtime and that
our building will be the first to be returned to service.
As many of you recall from last time, it is likely to get quite cold in
the lab. Over and above our personal discomfort, we expect that the
areas that are most likely to be affected will include the ebeam
lithography tools, resist coat, and wet etch operations in room
temperature baths (BOE and 50:1 HF, in particular). It is my
understanding (subject to correction by more knowledgeable sources) that
the ASML tool should not be affected as long as its environmental
chamber can keep the tool at temperature.
We apologize for this outage and any inconvenience that it causes. Let
us know if you have any questions or concerns related to this steam outage.
Thank you for your continued support,
John
MEMS Start-up Adventures: The Good, the Bad, and the Ugly
Kurt Petersen
President and Co-Founder, Cepheid
Consulting Professor of Electrical Engineering, Stanford University
Abstract:
Many interesting stories happen during start-ups. Like the "outside air"
guy, who was allergic to "inside air" - how did we solve this sensitive
employment issue at NovaSensor? Also, what about the corporate chairman
who vowed to take my house and my car and make sure that I never worked
again? What about the lay-offs and the lawsuits? We will explain these
and other adventures including the successes, the failures, and the
strange incidents that happen in the real world of MEMS start-ups.
Maybe, we will also get some insights into how some start-ups succeed
and others don't.
Biography:
Kurt Petersen received his BS degree cum laude in EE from UC Berkeley in
1970. In 1975, he received a PhD in EE from the Massachusetts Institute
of Technology. Dr. Petersen established a micromachining research group
at IBM from 1975 to 1982, during which he wrote the review paper
"Silicon as a Mechanical Material," published in the IEEE Proceedings
(May 1982). This paper is still the most frequently referenced work in
the field of micromachining and microelectromechanical systems (MEMS).
Since 1982, Dr. Petersen has co-founded three successful companies in
micromachining technology, Transensory Devices Inc. in 1982, NovaSensor
in 1985, and Cepheid in 1996. All of these companies have become
technical and commercial leaders in the field of MEMS devices and
applications. Most recently, Cepheid was established with the mission of
commercializing advanced MEMS techniques and other technologies for
miniaturized, biomedical and microfluidic systems and instruments,
particularly in the area of fast, portable, automated nucleic acid (DNA)
analysis for diagnostic applications in the biomedical, environmental,
and food industries as well as for bio-warfare defense. Cepheid has
become a recognized industry leader in rapid DNA purification,
detection, and analysis.
Dr. Petersen has published over 100 papers, and has been granted over 25
patents in the field of micromachining. In 2001 he was awarded the IEEE
Simon Ramo Medal for his contributions to MEMS. Dr. Petersen is a member
of the National Academy of Engineering and is a Fellow of the IEEE in
recognition of his contributions to "the commercialization of MEMS
technology".
Speaker: Albert Lin, Department of Electrical Engineering
Advisor: Professor H.-S. Philip Wong
Associate Advisor: Professor Subhasish Mitra
Date: Friday, February 12, 2010
Time: 3:30PM
Location: Packard 202
Abstract
Carbon Nanotube Field Effect Transistor (CNFET) technology has
received a lot of attention in the past few years as a promising
candidate for future integrated circuits, due in part to its potential
for ballistic transport and excellent intrinsic delay. However, to
realize the potential of CNFETs, carbon nanotube (CNT) technologies
that are scalable and robust must be developed. Such scalable carbon
nanotube technologies are presented here, from carbon nanotube
material synthesis to circuit fabrication.
In particular, four main achievements are discussed: (1) Wafer-scale
aligned CNT growth, delivering high-density, "nearly-perfectly"
straight CNTs; (2) Wafer-scale CNT Transfer, enabling independent
optimization of growth and device fabrication processes; (3) VLSI-
compatible device and circuit fabrication, achieving repeatable and
reliable wafer-scale integration; and (4) ACCNT (pronounced as
"accent"), a VLSI-compatible metallic-CNT tolerant design methodology,
achieving robust circuits despite imperfect CNT materials. Using these
techniques, CNT transistors, inverters, NANDs, and other logic gates
and small circuits are experimentally demonstrated. These four
contributions propel carbon nanotube technology forward towards the
vision of robust large-scale carbon nanotube circuits.
Philip Stephanou, Ph.D.
Co-Founder, Harmonic Devices, Inc.
Tuesday, Feb 9, 2010
Allen 101X 4:00–5:00pm
Abstract:
Electromechanical frequency control components such as quartz crystals
and surface or bulk acoustic wave (SAW or BAW) devices are ubiquitous as
signal processing elements in electronic communication, computing and
information technology systems. Billions of these components are
manufactured annually to sate the global needs of the commercial,
industrial, and defense sectors. Contemporary demands for low-cost,
highly-integrated portable wireless communication solutions provide the
greatest incentive in terms of potential technological, economic and
social impact to continue innovating passive electro-acoustic devices
such as oscillator crystals and bandpass filters. This talk will review
the evolution of and current state-of-the-art in MEMS resonators and
introduce Harmonic Devices Inc., a startup company founded to
commercialize thin-film piezoelectric RF MEMS technology.
Philip Stephanou, Ph.D.
Co-Founder, Harmonic Devices, Inc.
Tuesday, Feb 9, 2010
Allen 101X 4:00–5:00pm
Abstract:
Electromechanical frequency control components such as quartz crystals
and surface or bulk acoustic wave (SAW or BAW) devices are ubiquitous as
signal processing elements in electronic communication, computing and
information technology systems. Billions of these components are
manufactured annually to sate the global needs of the commercial,
industrial, and defense sectors. Contemporary demands for low-cost,
highly-integrated portable wireless communication solutions provide the
greatest incentive in terms of potential technological, economic and
social impact to continue innovating passive electro-acoustic devices
such as oscillator crystals and bandpass filters. This talk will review
the evolution of and current state-of-the-art in MEMS resonators and
introduce Harmonic Devices Inc., a startup company founded to
commercialize thin-film piezoelectric RF MEMS technology.
>Date: Tue, 09 Feb 2010 10:13:07 -0800
From: Peche Turner <peche@cs.stanford.edu>
To: faculty-plus@cs.Stanford.EDU
Subject: [Fwd: flyer re: donating laptops]
Hi all,
Many of us received a flyer about donating old laptops this morning. The
person listed is no longer affiliated with Stanford and I don't believe he
has any permission to be doing this.
Please do not offer him any of our laptops.
Reminder: any assets purchased with Stanford funds must be disposed of
via the Stanford Property Office, see your admins for assistance.
Thanks,
Peche
--
Peche Turner
Department Manager
Computer Science
Stanford University
(650) 723-5396
Just a reminder that there is a Process Clinic today (Monday) from 2-4
pm in the cubicle area outside of Maureen's office. Staff and senior
labmembers will be on hand to answer questions and brainstorm ideas to
address process issues. Bring your ideas, process questions, your
process runsheets, device layouts, and whatever else.
Your SNF staff
--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu
Thanks!
Stanford University PhD Dissertation Defense
Ying Chen (mihuhou@stanford.edu)
Research Advisor: Yoshio Nishi
Department of Electrical Engineering
Time: Monday, February 8th, @ 10:00 am
(refreshments served at 9:45 am)
Location: CISX Auditorium
ABSTRACT
Dye-sensitized Solar Cells (DSCs) have become a popular research topic
because of their low-cost, high-efficiency solar energy conversion. While
nanoparticle cell is currently the most efficient and stable DSC, nanowire
cells have shown some significant advantage that would make them superior to
nanoparticle cells. One such advantage is the fast and direct electron
transport, which was reported to be several hundred times faster than
trap-limited diffusion in nanoparticle cells, which can lower device
efficiency caused by electron-hole recombination. The efficiency of current
nanowire cells is primarily limited by the insufficiency of their internal
surface area due to the mechanical weakness of nanowire structures.
One solution to strengthen the nanowire structure is to build a framework
where individual nanowires are connected and prevented from clustering, so
as to increase the internal surface area and the efficiency of the solar
cell. Nanoframes containing 20nm diameter TiO2 nanowire arrays were
synthesized with polymer templates via cathodic Sol-Gel deposition followed
by 450oC sintering. Dye-sensitized Solar Cells based on this nanoframe were
fabricated and the effects of the top cover in the nanoframe, which is the
only difference between nanoframe cells and nanowire cells, were
investigated. The results show that the top cover does not prevent the I-
and I3- ions underneath from diffusing freely in the electrolyte and causes
no deterioration of the cell performance. The nanoframe cell is a promising
device in which nanowire arrays are strengthened and the effective internal
surface area have the potentiality to be increased without sacrificing the
advantages of nanowire cell compared to nanoparticle cell.
Due to additional work required to tied the new Nano building into the
campus facilities, the steam system to the area of campus including SNF
will be shut down from Friday, 2/12 at 10 am to Tuesday morning, 2/16 at
6 pm (see http://bgm.stanford.edu/groups/build_maint/plannedshutdowns)
Unfortunately, this means that there will be no temperature or humidity
control in the lab. Although this should have no effect on the
operation of most (if not all) systems in the lab, this could have a
significant effect on temperature sensitive operations, namely:
photolithography (resist coating, contact align exposure, develop) and
wet etching (non-temperature controlled baths, such as HF and BOE.)
We are working to see what might be done to minimize the impact on the
lab, but please be aware of this and try to plan your critical
experiments accordingly.
Your SNF Staff
I'd like to try my new process on a 300 nm SiO2 wafer (1-100 ohm/sq). If anyone plans to grow 300 nm SiO2 on 1-100 ohm/sq Si wafers (N or P type), I wonder if I could get one.
Thank you.
Regards,
Yoonyoung
There is a little WaveTek step attenuator in Allen 152 that would appear
to go up to 81 dB of attenuation with BNC in and out connectors on each
side. It's on the right end of the big rarely used rack at about
knee-height. There are also, I believe, some nice Hewlett-Packard
attenuators up in Tom Lee's circuit lab in Allen 219 that have the fancy
little SMA (I think) connectors. It would not surprise me to find that
they have both fixed and stepped attenuators. I don't know who would be
best to ask about borrowing one or more for a short time.
Good luck,
John
Philip Stephanou, Ph.D.
Co-Founder, Harmonic Devices, Inc.
Tuesday, Feb 9, 2010
Allen 101X 4:00–5:00pm
Abstract:
Electromechanical frequency control components such as quartz crystals
and surface or bulk acoustic wave (SAW or BAW) devices are ubiquitous as
signal processing elements in electronic communication, computing and
information technology systems. Billions of these components are
manufactured annually to sate the global needs of the commercial,
industrial, and defense sectors. Contemporary demands for low-cost,
highly-integrated portable wireless communication solutions provide the
greatest incentive in terms of potential technological, economic and
social impact to continue innovating passive electro-acoustic devices
such as oscillator crystals and bandpass filters. This talk will review
the evolution of and current state-of-the-art in MEMS resonators and
introduce Harmonic Devices Inc., a startup company founded to
commercialize thin-film piezoelectric RF MEMS technology.
Biography:
Dr. Philip Stephanou is an expert in the area of piezoelectric MEMS
design, fabrication and testing. Philip holds a Ph.D. in Mechanical
Engineering from the University of California at Berkeley where, as a
member of the Berkeley Sensor and Actuator Center (BSAC), he co-invented
a new class of thin-film aluminum nitride (AlN) based electromechanical
resonators and filters. He has developed a variety of AlN MEMS resonator
topologies and received a best paper award at the 2006 IEEE Ultrasonics
Symposium for developing the first thin-film, lithography-defined,
fundamental mode MEMS resonators to break the GHz barrier. In 2005,
Philip co-founded Harmonic Devices, Inc. (HDI) in order to commercialize
multi-frequency bandpass filter solutions based on the AlN contour mode
resonator technology. HDI has received funding from NASA, DARPA and NSF
as well as commercial entities. Philip co-founded Verreon, Inc. in 2009.
Intercalation in polymer:fullerene organic solar cells
Nicky Cates
Material Science and Engineering
McGehee Group
Polymer:fullerene bulk heterojunction (BHJ) organic solar cells have achieved power conversion efficiencies up to 7.9% and are attracting a great deal of attention as a potential low-cost alternative to traditional inorganic photovoltaics. Fullerene intercalation between the side chains of conjugated polymers has recently been demonstrated in some polymer:fullerene BHJ solar cells. We investigate intercalation in the crystalline polymer (pBTTT) and the amorphous polymer (MDMO-PPV) using a variety of techniques including X-ray diffraction (XRD), photoluminescence (PL) and current-voltage measurements. This work demonstrates that intercalation can be controlled by adjusting the fullerene size and side-chain branching, clarifies the effect of intercalation on solar-cell properties and explains why intercalation may be responsible for the significant increase in the MDMO-PPV hole mobility when it is blended with phenyl-c61-butyric acid methyl ester (PC61BM).
Stanford University PhD Dissertation Defense
Ying Chen (mihuhou@stanford.edu)
Research Advisor: Yoshio Nishi
Department of Electrical Engineering
Time: Monday, February 8th, @ 10:00 am
(refreshments served at 9:45 am)
Location: CISX Auditorium
ABSTRACT
Dye-sensitized Solar Cells (DSCs) have become a popular research topic
because of their low-cost, high-efficiency solar energy conversion. While
nanoparticle cell is currently the most efficient and stable DSC, nanowire
cells have shown some significant advantage that would make them superior to
nanoparticle cells. One such advantage is the fast and direct electron
transport, which was reported to be several hundred times faster than
trap-limited diffusion in nanoparticle cells, which can lower device
efficiency caused by electron-hole recombination. The efficiency of current
nanowire cells is primarily limited by the insufficiency of their internal
surface area due to the mechanical weakness of nanowire structures.
One solution to strengthen the nanowire structure is to build a framework
where individual nanowires are connected and prevented from clustering, so
as to increase the internal surface area and the efficiency of the solar
cell. Nanoframes containing 20nm diameter TiO2 nanowire arrays were
synthesized with polymer templates via cathodic Sol-Gel deposition followed
by 450oC sintering. Dye-sensitized Solar Cells based on this nanoframe were
fabricated and the effects of the top cover in the nanoframe, which is the
only difference between nanoframe cells and nanowire cells, were
investigated. The results show that the top cover does not prevent the I-
and I3- ions underneath from diffusing freely in the electrolyte and causes
no deterioration of the cell performance. The nanoframe cell is a promising
device in which nanowire arrays are strengthened and the effective internal
surface area have the potentiality to be increased without sacrificing the
advantages of nanowire cell compared to nanoparticle cell.
Sarves Verma
Advisor: Professor Krishna Saraswat
Department of Materials Science & Engineering
Department of Electrical Engineering
Wednesday, February 10th, 2010, 1:00 pm
CISX Auditorium
(Refreshments served at 12:45pm)
Abstract
The conventional Flash memory faces two critical obstacles in the future: Density and Voltage scaling. Density is associated with scaling the gate length. The gate length cannot be reduced beyond a point because it requires a commensurate gate stack, specifically, tunnel oxide scaling for maintaining good gate control and short channel effects. However, the gate-tunnel oxide (GTO) reduction has a practical lower bound of ~ 7-9nm (depending upon NAND or NOR) due to leakage and data retention constraints. Below this GTO thickness, irrespective of how inter-poly dielectric (referred as ONO) is scaled, the electric field across it during charge retention increases, leading to unacceptable levels of tunneling current. The second major challenge with scaling is to reduce the programming and erase operation voltages. The usual operation voltages for these processes are much greater (15-18 Volts). With scaling, it is imperative for operating voltages to reduce. Typically, read voltages are low, while erase and program operations stress the charge pump requirements and dictate the maximum voltages. The major impediment in erase voltage scaling is, once again, the inability to scale the gate oxide. Recently, engineered tunnel barriers were proposed as solutions to scaling gate oxide. It is postulated that engineered barriers offer faster program/erase yet maintain excellent retention. However, a detailed characterization of engineered tunnel dielectrics and a deeper understanding of the erase/program mechanism are sought to establish its implementation.
In the first half of the talk, we perform simulations to establish the feasibility of tunnel barriers under Flash memory device constraints. We look at different higher-K materials as a replacement for SiO2 and perform global optimization over different materials. This is first done under absence of traps in these materials. Later the assumptions are relaxed and traps are incorporated in these materials. In the second part of the talk, we implement engineered tunnel barriers based on the simulation results. However, it is observed that presence of traps in these materials degrades performance. Retention loss and endurance degradation are identified as two major problems, hindering implementation and scaling. In the third and final part, we discuss solutions to these problems. Fluorine is well known as a passivating agent for traps in high-K dielectrics. We incorporate fluorine in engineered tunnel stacks and show electrical & physical characterization results to emphasize its advantages. Finally, alternative tunnel barrier structures and materials are discussed to continue scaling of gate dielectrics.
Nima Ghalichechian, Ph.D.
Senior Principal MEMS Engineer, FormFactor Inc.
Tuesday, Feb 2, 2010
Allen 101X 4:00–5:00pm
Abstract:
The design, fabrication, and characterization of a rotary micromotor
supported on microball bearings developed at the University of Maryland
will be presented. This has been the first demonstration of a rotary
micromachine with a robust mechanical support provided by
microball-bearing technology. One key challenge in the realization of a
reliable micromachine is the development of a bearing that would result
in high stability, low friction, and high resistance to wear. A
six-phase, rotary, bottom-drive, variable-capacitance micromotor is
designed, simulated, and fabricated on silicon using benzocyclobutene
low-k dielectric films. A characterization methodology is developed to
measure and extract the angular displacement, velocity, acceleration,
torque, mechanical power, coefficient of friction, and frictional force
through non-contact techniques. A top angular velocity of 517 rpm
corresponding to the linear tip velocity of 324 mm/s is measured.
Measurement of the transient response of the rotor indicated that the
torque is 5.62+/-0.5 micro N-m. Such a rotary micromotor can be used in
developing micropumps which are highly demanded microsystems for fuel
delivery, drug delivery, cooling, and vacuum applications. Examples of
successful applications of this work will be presented.
Dear Labmembers,
A black and purple canvas zippered pencil/pen case has been sitting on the bench outside the lab for a couple of days. If this is yours please come to my cubicle and pick it up.
Thanks,
Maureen
Maureen Baran
Stanford Nanofabrication Facility
Lab Services Administrator
mbaran@stanford.edu
650-725-3664
