[p5000etch-pcs] Tenerife, Spain, Conference

ICCE-21  Tenerife, Canary Islands, Spain, July 21-27, 2013

(the “Hawaii” of Europe)

 

21^st  Annual International Conference on Composites or Nano Engineering

www.icce-nano.org

 

re:  Call for ICCE-21 papers and thanks to participants of previous ICCE conferences

 

Dear p5000etch-pcs@snf.stanford.edu :

 

 

(item 1) we are still accepting NEW paper titles  for ICCE-21, July 21-27, 2013, Tenerife, Canary Islands, Spain (also known as the Hawaii of Europe)..  All areas of Composite materials, metals, polymers, ceramics, or nano materials  and all kinds of fibers research, will be welcomed, among other current hot topics such as those in bio nano, energy materials, green engineering, natural fibers, and, chemistry materials,  computational materials and experimental mechanics etc..   Please inform many more interested professors, researchers, especially students, and junior faculty members, who need visibilities to present papers.  Interested authors who plan to travel to Tenerife to attend ICCE-21, should submit tentative paper titles immediately,  and then submit detailed two-page short papers as soon as possible to David Hui.

 

 

(item 2) Participants who plan to travel to Tenerife, should submit detailed two-page short papers (each page two-columns) with  as many graphs as possible, to show results  are peered reviewed and will appear in proceedings, upon payment of registration fee and attendance of ICCE-21.   Further, “all” full-length version of these short papers (with paper title change) will also be peered reviewed and published in selected journals.   Thus, all participants will have journal papers as benefits of coming to ICCE-21, Tenerife, Spain.  There is no need for full-length paper, but we encourage you to submit full-length papers, please do so during or immediately after the conference.   Due to budgetary constraints, there is no financial support. 

 

 

(item 3)  the ICCE-21 pre-registration fee of US$390 before May 21, 2013, is reasonable for five-day conference in Spain, and student early pre-registration fee of US$200 is even more reasonable.  As usual, please contact D. Hui for the excellent  affordable venue hotel in Tenerife, Spain.  This conference has received over 210,000 citations from Google Search, and has been attended by numerous experts in the fields as evidenced by over 30 NAE or NAS keynote lectures. The Tenerife destinations is extremely popular and high season for tourists in Europe.  Please go to   www.icce-nano.org and click “why go to Tenerife?”)

 

 

Season’s Greetings.

 

David Hui

 

David Hui

Chair ICCE-21 Tenerife, Canary Islands, Spain

dhui@uno.edu

 

www.icce-nano.org

 

December 21, 2012 

 

 

 

 

 

 

 

 

 

 

 

 

 

we have significantly downsized our e-mailing list, please help to reduce this list further

 

to delete write delete

SNF: Shut Down for Winter Closure

Dear Labmembers --

SNF is officially closed for business. Doors reopen on Tuesday, Jan. 8
at 7 am.

Happy holidays and see you next year!

Your SNF Staff

--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
Paul G. Allen Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu

MEMS engineer opening in Northern Europe

Dear Labmembers,

Fairchild Semiconductor has two positions opening up for a MEMS foundry Engineer and MEMS Process Technician (or Jr. Engineer), to work in a fab in Northern Europe. The positions would require spending ~75% time in Northern Europe.

Please let me know if you are interested.

Shasha

Sloped Via Etch

Hi All,

Before we go on vacation, I just wanted to ask if anyone had measured Step Profile for O2, CHF3 Oxide Etch on mrc? I need to have sloped Via Etch for contaminated process. Because next step is evaporative dep for lift off. Any other suggestions would also be helpful.

-Jyotindra

Today's the Day - Winter (Holiday) Party from 1:00 to 3:00P on the 1st floor of the Allen Building

Dear All,

 

Today is our Winter (Holiday) party from 1:00P to 3:00P.  Please make time in your busy schedule to come down and have a drink (soda or water – you decide) with your co-workers / co lab members.

 

The fun begins on the first floor of the Allen building next to the Litho (yellow) area of the lab at 1:00P.

 

Thank you,

 

Maureen

 

From: Maureen Baran [mailto:mbaran@stanford.edu]
Sent: Monday, December 10, 2012 11:58 AM
To: cis-building@cis.stanford.edu; labmembers@snf.stanford.edu
Subject: Holiday Party - Tuesday, December 18th from 1:00 to 3:00
Importance: High

 

MARK YOUR CALENDAR!!!

 

Dear All,

 

We are planning a wonderful Holiday party, Tuesday, December 18^th from 1:00 to 3:00.  Please plan accordingly and give yourself some well-deserved time to enjoy a cup of cheer and more with your fellow Allen Building Dwellers / SNF Lab Members to reminisce about 2012 or your holiday plans.

 

Maureen

Continuing good HD oxide, even across a chamber clean

Recipe "HDP-SiO2"

We ran 6 wafers targeting 5000 A, 2 before a chamber plasma clean, 4 after.  Measurements this run were 55 pt Woollam.

The dep rate and uniformity continue to be ~1%.  The current dep rate estimate is 27.66 A/sec, consistent with previous values of

27.72 and 27.58.  Remember to include the 6 sec of "strike" in the rate calculations

The 1st wafer after the clean was 0.68% thicker than the averages (= 2 sigma of wafer avgs, nearly a significant difference).

Those few interested in this spreadsheet, please ask.

Douglas Tham participated in the depositions and measurements.

Thanks to Jim McVittie, Nancy and Elmer, and to SNF for a marvelous new tool.

Also to Ed Myers for the Woollam, making these measurements possible.

jim

Re: Problem p5000etch SNF 2012-12-17 13:55:45: chamber A is down

Reseated control cable and homed throttle valve. Chexcked
pressure at 30 and 300 mt w/out problem.

SNF LAB BINS WILL BE EMPTIED!!!

Dear labmembers --

SNF lab bins WILL BE EMPTIED starting on shutdown, Thursday at 7 am. If
you want to keep your bins and items in your bins over the shutdown, you
will need to contact Maureen Baran (mbaran@snf) or Aubrey
(aubreym@stanford.edu) about renewing your subscription for the year.

Any bins which do not have active subscriptions WILL BE EMPTIED by staff.

Your SNF staff

--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
Paul G. Allen Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu

Problem p5000etch SNF 2012-12-17 13:55:45: chamber A is down

throttle valve is not responding... Elmer is on the case.

silicon wet etching question

Dear Labmembers,

I have a question for you on silicon wet etching. I would like to
create an array of slightly tilted ramp surfaces in silicon. The tilted
surfaces are 50 um by 50 um with a bottom surface that is tilted by 3
degree from wafer surface, so that one side has a depth of 2.5 um and
the other side has a depth of zero. The small surface should be
optically smooth for optical purposes. I wonder if this can be done
simply by patterning and wet etching silicon using KOH etch with a
silicon wafer that is cut 3 degree off (111) orientation. It appears to
be an easy task to do, since the starting surface is so close to the
final surface (only etch down 2.5 um on one side of the ramp). But I
have been warned that it may not be easy to do.

Has anyone done this before? Do you think this approach would work?
Would the final surface be optical quality, or the ramped surface might
have a lot of steps? Thanks.

Merry Christmas!

Ben

Reminder: Labmembers' Mtg Today, 10 am in the Auditorium

Dear Labmembers --

The Labmembers' meeting is today, Monday, Dec. 17. It will
be at 10 am in the AllenX Auditorium. The agenda will be as follows:

Intro/Overview: John Bumgarner
Clean Room Ops: Brett Huff
Epi update: Maurice
New Etcher Installation Update: Ed Myers
Renovation 2: Mary Tang
Labmember Survey Summary: Mary Tang
Badger Rollout: Michael Bell
Financials: Aubrey Martinez
Closing: John B

--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
Paul G. Allen Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu

Re: Problem p5000etch SNF 2012-12-14 21:15:34: Interface ribbon cable

Installed new interface ribbon cable..

Problem p5000etch SNF 2012-12-14 21:15:34: Interface ribbon cable

Temporary repairded the ribbon cable, will need to be change,
ribbon cable is rubbing on the load lock fore line tee valve.

Re: Problem p5000etch SNF 2012-12-14 14:54:44: chamber b

Vneted chanber and removed wafer chips on pedestal quartz,
Adjusted rotation and extension drop and pick up.

Re: Shutdown p5000etch SNF 2012-12-14 15:22:48: Robot Extension

Temporary repiared (solder broken wires) ribbon cable. Lugwig
needed the tool badly. Ribbon cable is part of the robot it move when
robot is moving to chamber axis.

Comment p5000etch SNF 2012-12-14 16:20:27: Update

The robot interface ribbon cable has broken wire, robot error
for extension position unknown. Need to make a new ribbon
cable.

Shutdown p5000etch SNF 2012-12-14 15:22:48: Robot Extension

Chamber B error saying Robot Extension position is not known.

Problem p5000etch SNF 2012-12-14 14:54:44: chamber b

Same wafer chipping problem (5 o'clock position). I guess I'm not going to use chamber B anymore. Left a sample out for staff inspection.

[Reminder] PhD Defense Announcement: Chia-Fang Chiang Tomorrow 10am, Hartley conference center

Stanford University Ph.D. Oral Examination – Dept. of Mechanical Engineering

 

Title:

Micromachined Temperature Compensated Pressure Sensor
Implemented Using a Multi-Sensor Integration Platform

 

Chia-Fang Chiang

Advisor: Professor Thomas W. Kenny

 

Date: Friday, December 14, 2012

Time: 10:00 am (refreshments at 9:45 am)

Location: Hartley conference center (Mitchell Earth Sciences) - Room 130

 

Abstract: 

 

Micromachined pressure sensors are widely used in our everyday lives: in automobiles they are implemented to monitor tire pressure and detect side crashes; in medical devices they are used to track blood pressure in the brain; and in navigation they are utilized to determine altitude and assist global positioning system (GPS) receivers. While the requirements for a pressure sensor vary depending upon the specific application, a common requirement is accurate sensing over a wide operating temperature range (-40 – 125 °C).

 

I will begin by introducing our capacitive pressure sensor design and demonstrating how it outperforms a piezoresistive pressure sensor with respect to temperature insensitivity. To further reduce temperature dependence, a high resolution resonant thermometer has been cofabricated with the capacitive pressure sensor, enabling the tracking of temperature fluctuations on the die and correction of the associated pressure error.

 

In the second half of the talk, I will discuss our development of a resonant pressure sensor. This is motivated by the emerging demand of altimeters which require high resolution (10Pa/meter). As the design is coupled to the die strain, the accuracy of the resonant pressure sensors is strongly influenced by errors induced by both temperature and package stress. We address this limitation with a multiple sensor solution where temperature and strain sensors are cofabricated to reduce the pressure sensor's temperature and package stress dependence, thus improving accuracy.

 

Throughout the talk, I will discuss the process flows enabling the fabrication of such structures. Key developments include time insensitive vapor etching of silicon dioxide with hydrofluoric acid to release structures as well as the fabrication of structures that can be driven and sensed in both in-plane (x,y) and out-of-plane (z) directions on either bulk silicon or SOI wafer substrates.

Badger VPN Issues

Michaell,

I have tired more than many times to get the VPN going, but no luck!

My account works fine, when I am in Stanford network. 

I have talked many users they have the same issues.

I am not going to local coffee house to reserve my tool time. 

This needs to be fixed, before lab starts using badger next year. 

Thank you for your attention.

Pradeep

On Sun, Dec 2, 2012 at 6:07 PM, Michael Bell <mikebell@stanford.edu> wrote:

Pradeep,

As a current user of Badger I'm sure you've been relieved to see that much of the look and feel of the application is identical to that of Coral and that there are a number of enhancements that benefit members and staff alike. In addition to the presentations a couple of months ago, more information on the conversion specifics will be available shortly. Rest assured that every effort is being made to make the transition as painless as possible.

It is true that Badger, like so many software resources at Stanford and elsewhere, restricts offsite access. Stanford does supply a VPN client that enables offsite use of the application in most cases. I understand that your employer has a particularly restrictive policy concerning this. I can certainly appreciate their concerns for the security of mission critical resources and would only add that, firewalls, data encryption and increasingly complex authentication strategies are a sometimes annoying, but inevitable consequence of the need for data and application security in the face of sophisticated threats. I have used the Stanford VPN successfully for years and have found it to be robust and reliable. I'm hopeful that most members, like myself, will find that offsite access from home, work or the local café will not be an issue.  

The good news on multiple accounts is that Badger can support functionality identical to that of Coral. We will have more information on this and other issues in the very near future.  Again, we are committed to making the conversion to Badger as seamless as possible and expect most members to find that the conversion will make the scheduling and use of equipment in Stanford's shared labs more convenient.

Regards,

Michael Bell

 

Shutdown Countdown: One week!

Dear Labmembers:

Shutdown in ONE WEEK (7 am Thurs, 12/20.)

- Your LAB BIN WILL BE REMOVED unless you inform staff!
(See http://snf.stanford.edu/cgi-bin/ezmlm-cgi?mss:5421:201212:ldjpkjnagmdabiecmjca)

- Tomorrow is the deadline for setting up new Badger accounts to ensure uninterrupted SNF access.
(See http://snf.stanford.edu/cgi-bin/ezmlm-cgi?mss:5432:201212:pcmggcgaalobimlandbm)

Thanks for your attention --


Your SNF staff

--   Mary X. Tang, Ph.D.  Stanford Nanofabrication Facility  Paul G. Allen Room 136, Mail Code 4070  Stanford, CA  94305  (650)723-9980  mtang@stanford.edu  http://snf.stanford.edu  

Re: Silicon cleaving

Emma Chisit?

fp

On Dec 12, 2012, at 11:26 AM, Liam O'Faolain wrote:

Dear Labmembers,

I have recently learned about this system- https://latticegear.com/store/cleaving-hardware/latticeax-with-eagle-eye-camera/. This appears to be a very precise means of cleaving silicon and potentially very useful to many of us. You may find a video of it in operaton here: http://www.youtube.com/watch?v=L0RXW8fVn4Q&feature=plcp

A sales representative from LatticeGear is planning to give me a demonstration of the system in the middle of January. If you are interested in attending, please let me know.

Yours,
Liam

--   Dr. William Whelan-Curtin (Liam O'Faolain)   Ginzton Laboratory, Nano Building  348 Via Pueblo Mall, Stanford CA 94305, USA.  http://www.nanophotonics.eu

Labmembers' Mtg - New Date: 12/17/12

Dear Labmembers --

The Labmembers' meeting has been postponed to Monday, Dec. 17.  It will be at 10 am in the AllenX Auditorium.  The agenda will be as follows:

Intro/Overview:  John Bumgarner
Clean Room Ops: Brett Huff
Epi update: Maurice
New Etcher Installation Update: Ed Myers
Renovation 2: Mary Tang
Labmember Survey Summary: Mary Tang
Badger Rollout: Michael Bell
Financials: Aubrey Martinez
Closing:  John B

--   Mary X. Tang, Ph.D.  Stanford Nanofabrication Facility  Paul G. Allen Room 136, Mail Code 4070  Stanford, CA  94305  (650)723-9980  mtang@stanford.edu  http://snf.stanford.edu  

Silicon cleaving

Dear Labmembers,

I have recently learned about this system- https://latticegear.com/store/cleaving-hardware/latticeax-with-eagle-eye-camera/. This appears to be a very precise means of cleaving silicon and potentially very useful to many of us. You may find a video of it in operaton here: http://www.youtube.com/watch?v=L0RXW8fVn4Q&feature=plcp

A sales representative from LatticeGear is planning to give me a demonstration of the system in the middle of January. If you are interested in attending, please let me know.

Yours,
Liam

--   Dr. William Whelan-Curtin (Liam O'Faolain)   Ginzton Laboratory, Nano Building  348 Via Pueblo Mall, Stanford CA 94305, USA.  http://www.nanophotonics.eu

Re: Problem p5000etch SNF 2012-12-10 22:45:48: Ch.B shut down

clamp replaced and 8 wafers cycled without incident.

SNF Badger Conversion Instructions and December Timeline and More

2^nd Notice – Please make every effort to get your application done.

 

Dear SNF Lab Members:

 

As most of you know SNF is in the process of converting from the Coral application to Badger Lab Management Software. Members will use Coral until the start of the holiday break and use Badger after the break. Reservations for after the break can be made in Badger with the usual reservation horizons. Many members already have Badger accounts and know that the look and feel of Badger is similar to Coral. New Badger users will have no trouble performing all of their normal functions. Our hope is to make this transition as simple as possible. It is; however, critical that all members read the information at the website below and move quickly to follow the instructions.

 

https://www.stanford.edu/group/snf/Badger/SNF-Conversion.html

 

Important Dates -

 

12-14   Final day to complete your application and verify your data in Coral and Badger.

12-21   Lab Closes – Coral use ends.

1-8       Lab Reopens – Badger is used over the break for reservations starting on the 8^th.

 

Regards,

 

The SNF Conversion Team

 

Shutdown Countdown is 8 Days: Remember YOUR LAB BIN!

Dear labmembers --

Shutdown in EIGHT days (7 am Thurs, 12/20.) Your LAB BIN WILL BE
REMOVED unless you inform staff!
(See
http://snf.stanford.edu/cgi-bin/ezmlm-cgi?mss:5421:201212:ldjpkjnagmdabiecmjca)

Your SNF Staff

Vendor suggestion for fired ceramic PCB

Dear Lab members,

I am looking for a vendor that has the ability to make a two layer PCB
on fired ceramic. The few I've talked to today use a ceramic-PTFE
laminate but that won't work for my application. Does anyone have any
recommendations?

Thanks,
Karthik

---------------------------
Karthik Balakrishnan
karthikb@stanford.edu

PhD Candidate, Stanford University

Department of Aeronautics and Astronautics
Hansen Experimental Physics Labs
452 Lomita Mall Room 223
Stanford, California 94305

Problem p5000etch SNF 2012-12-10 22:45:48: Ch.B shut down

The wafer was broken inside the chamber.

Re: Problem p5000etch SNF 2012-12-10 16:35:34: Chamber B still chipping wafers

Vented chamber and checked and verfied wafer placement into
chamber B good(wafer is center) found the small wafer chip
on top of the pedestal quartz right on the wafer flat and wafer chip
look thin for a standard silicon wafer.

Problem p5000etch SNF 2012-12-10 16:35:34: Chamber B still chipping wafers

It chipped 1 out of 5 wafers at the same location as the previous user.

Re: Good results with HD_SiO2

Jim,

Today, I measured the peak wafer temperature for a 3 min HDP nitride run using the temperature label method, which we commonly use in the etch systems. The peak temperature is > 107C but < 121C. Remember that the chuck temperature is set to 90C. The heating is from ions coming from the ICP plasma which is running at 1000w. I expect the oxide process to reach a similar peak temperature. I will measure the oxide case later in the wk. Jim

----- Original Message -----
From: "jim kruger" <jimkruger@yahoo.com>
To: "Sebastian J. Osterfeld" <sebastian.j.osterfeld@magarray.com>
Cc: "Douglas Tham" <tham@siliciumenergy.com>, HD-pcvd@SNF.stanford.edu, labmembers@snf.stanford.edu
Sent: Friday, December 7, 2012 7:20:13 PM
Subject: Re: Good results with HD_SiO2



The nominal chuck temperature is 90C, wafer believed less than 100C.

The wafer is RF Biased to give some ion bombardment during deposition.



jim






From: Sebastian J. Osterfeld <sebastian.j.osterfeld@magarray.com>
To: jim kruger <jimkruger@yahoo.com>
Cc: Douglas Tham <tham@siliciumenergy.com>; HD-pcvd@SNF.stanford.edu; labmembers@snf.stanford.edu
Sent: Friday, December 7, 2012 7:10 PM
Subject: Re: Good results with HD_SiO2




Hi Jim,

What is the wafer temperature during the SiO2 deposition?

Thanks!
Sebastian




From: "jim kruger" <jimkruger@yahoo.com>
To: HD-pcvd@SNF.stanford.edu, labmembers@snf.stanford.edu
Cc: "Douglas Tham" <tham@siliciumenergy.com>
Sent: Friday, December 7, 2012 12:02:26 PM
Subject: Good results with HD_SiO2




Good results for HD_SiO2.
I find that the uniformity and reproducibility of rate and index are all better than 1%


I also find that Nanospec(5 pt) and Woollam(9 pt) averages agree to better than 1%


The key to predicting thickness is adding the 6 seconds of the "Light" step to the total deposition time.


I included data from thickness' 56 nm to 677 nm and from factory and site acceptance as well as depositions logged by "wslee" and my own 3 depositions.


The rate for HD_SiO2 is 27.58 A/sec, +/- 1%. Remember to account for the 6 seconds of strike.


If interested, I can e-mail my spreadsheet.


Please log your results and send me your data for "HD_SiO2". Send dry etch, and especially wet etch rates as well.


Any one interested in a recipe for lower rate for control of thinner films? I predict (10.3 + 6) seconds for a 450 Ang. film.


jimkruger

Re: Problem p5000etch SNF 2012-12-09 17:06:34: chipped wafers

Wafer clamp looks OK. Adjusted wafer placement in chamber and cycled 8 wafers with no problems.

Holiday Party - Tuesday, December 18th from 1:00 to 3:00

MARK YOUR CALENDAR!!!

 

Dear All,

 

We are planning a wonderful Holiday party, Tuesday, December 18^th from 1:00 to 3:00.  Please plan accordingly and give yourself some well-deserved time to enjoy a cup of cheer and more with your fellow Allen Building Dwellers / SNF Lab Members to reminisce about 2012 or your holiday plans.

 

Maureen

Labmembers' Meeting, 10 am Thursday, 12/13

Greetings labmembers --

There will be a Labmembers' meeting held this Thursday, Dec. 13, at 10
am in the AllenX Auditorium. The agenda includes (though subject to
change):

1. Opening remarks: Overview, intro to new staff/org structure -- John
Bumgarner
2. Financials and Badger Rollout: John B, Aubrey Martinez
3. New Tool Installation Update: Ed Myers
4. Clean Room Ops: Brett Huff
5. Renovation/Renovation II and Labmember Survey Summary: Mary Tang
6. Closing remarks: John B

Your SNF Staff

--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
Paul G. Allen Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu

Problem p5000etch SNF 2012-12-09 17:06:34: chipped wafers

Was doing oxide etch in chamber B and 5 of my 7 wafers had a large chip in the 5 o'clock position (assuming flat is in the 12 o'clock) after the came out. Clamp might be too strong?

Re: Good results with HD_SiO2

The nominal chuck temperature is 90C, wafer believed less than 100C.

The wafer is RF Biased to give some ion bombardment during deposition.

jim

---

From: Sebastian J. Osterfeld <sebastian.j.osterfeld@magarray.com>
To: jim kruger <jimkruger@yahoo.com>
Cc: Douglas Tham <tham@siliciumenergy.com>; HD-pcvd@SNF.stanford.edu; labmembers@snf.stanford.edu
Sent: Friday, December 7, 2012 7:10 PM
Subject: Re: Good results with HD_SiO2

Hi Jim,

What is the wafer temperature during the SiO2 deposition?

Thanks!
Sebastian

---

From: "jim kruger" <jimkruger@yahoo.com>
To: HD-pcvd@SNF.stanford.edu, labmembers@snf.stanford.edu
Cc: "Douglas Tham" <tham@siliciumenergy.com>
Sent: Friday, December 7, 2012 12:02:26 PM
Subject: Good results with HD_SiO2

Good results for HD_SiO2.

I find that the uniformity and reproducibility of rate and index are all better than 1%

I also find that Nanospec(5 pt) and Woollam(9 pt) averages agree to better than 1%

The key to predicting thickness is adding the 6 seconds of the "Light" step to the total deposition time.

I included data from thickness' 56 nm to 677 nm and from factory and site acceptance as well as depositions logged by "wslee" and my own 3 depositions.

The rate for HD_SiO2 is 27.58 A/sec, +/- 1%. Remember to account for the 6 seconds of strike.

If interested, I can e-mail my spreadsheet.

Please log your results and send me your data for "HD_SiO2". Send dry etch, and especially wet etch rates as well.

Any one interested in a recipe for lower rate for control of thinner films?   I predict (10.3 + 6) seconds for a 450 Ang. film.

jimkruger

Re: Good results with HD_SiO2

Hi Jim,

What is the wafer temperature during the SiO2 deposition?

Thanks!
Sebastian

---

From: "jim kruger" <jimkruger@yahoo.com>
To: HD-pcvd@SNF.stanford.edu, labmembers@snf.stanford.edu
Cc: "Douglas Tham" <tham@siliciumenergy.com>
Sent: Friday, December 7, 2012 12:02:26 PM
Subject: Good results with HD_SiO2

Good results for HD_SiO2.

I find that the uniformity and reproducibility of rate and index are all better than 1%

I also find that Nanospec(5 pt) and Woollam(9 pt) averages agree to better than 1%

The key to predicting thickness is adding the 6 seconds of the "Light" step to the total deposition time.

I included data from thickness' 56 nm to 677 nm and from factory and site acceptance as well as depositions logged by "wslee" and my own 3 depositions.

The rate for HD_SiO2 is 27.58 A/sec, +/- 1%. Remember to account for the 6 seconds of strike.

If interested, I can e-mail my spreadsheet.

Please log your results and send me your data for "HD_SiO2". Send dry etch, and especially wet etch rates as well.

Any one interested in a recipe for lower rate for control of thinner films?   I predict (10.3 + 6) seconds for a 450 Ang. film.

jimkruger

Re: Good results with HD_SiO2

Thanks for that Jim.

Also Big thanks to Jim Mcvitte for all the effort installing and bringing up the tool. 

Attached is the SIMS from Applied Materials, indicating that no metal or other contamination in the chamber.

I am pretty surprised given that it is a low temp tool and contaminated tool. 

 

Also attached is also the AFM roughness Images for the tool on SiNx and SiOx for 1000A.

Enjoy 

Pradeep 

On Fri, Dec 7, 2012 at 12:02 PM, jim kruger <jimkruger@yahoo.com> wrote:

Good results for HD_SiO2.

I find that the uniformity and reproducibility of rate and index are all better than 1%

I also find that Nanospec(5 pt) and Woollam(9 pt) averages agree to better than 1%

The key to predicting thickness is adding the 6 seconds of the "Light" step to the total deposition time.

I included data from thickness' 56 nm to 677 nm and from factory and site acceptance as well as depositions logged by "wslee" and my own 3 depositions.

The rate for HD_SiO2 is 27.58 A/sec, +/- 1%. Remember to account for the 6 seconds of strike.

If interested, I can e-mail my spreadsheet.

Please log your results and send me your data for "HD_SiO2". Send dry etch, and especially wet etch rates as well.

Any one interested in a recipe for lower rate for control of thinner films?   I predict (10.3 + 6) seconds for a 450 Ang. film.

jimkruger

Good results with HD_SiO2

Good results for HD_SiO2.

I find that the uniformity and reproducibility of rate and index are all better than 1%

I also find that Nanospec(5 pt) and Woollam(9 pt) averages agree to better than 1%

The key to predicting thickness is adding the 6 seconds of the "Light" step to the total deposition time.

I included data from thickness' 56 nm to 677 nm and from factory and site acceptance as well as depositions logged by "wslee" and my own 3 depositions.

The rate for HD_SiO2 is 27.58 A/sec, +/- 1%. Remember to account for the 6 seconds of strike.

If interested, I can e-mail my spreadsheet.

Please log your results and send me your data for "HD_SiO2". Send dry etch, and especially wet etch rates as well.

Any one interested in a recipe for lower rate for control of thinner films?   I predict (10.3 + 6) seconds for a 450 Ang. film.

jimkruger

Company for placing solder balls

Dear Lab members,
Good afternoon.
I am looking for a company for placing solder balls like the picture as
attached.
If you have any information about this kind of company, please let me know.
Thank you very much.
Best regards,
Chienliu
-------------------------------------------------
Chienliu Chang, Ph.D.

Room 104
Ginzton Laboratory
Center for Nanoscale Science & Engineering
Stanford University
348 Via Pueblo, Stanford, CA 94305-4088

Phone: 650-725-2265
Email: clchang6@stanford.edu
clchang6@ntu.edu.tw
-------------------------------------------------

Countdown to Shutdown: TWO weeks!

Dear Labmembers --

REMINDER: Lab shuts down at 7 am THURSDAY, Dec. 20. Lab reopens Tuesday, Jan. 8, at
7 am.

REMOVE EVERYTHING: from WIP shelves and common storage by shutdown.

LAB BINS & LOCKERS: All personal items MUST be removed from lab bins and lockers by
shutdown, unless you renew subscriptions (new policy, below).
Contact mbaran@snf.stanford.edu or mahnaz@snf.stanford.edu to get your
bin or locker tagged. Bins or lockers without tags will be emptied at shutdown.
Be aware that SNF is not responsible for valuables left during shutdown.


NEW BIN & LOCKER POLICY: Bin/locker fees will be charged when assigned, for rental
through Dec. 2013. So, in January, it will be 12 months of fees (e.g., $120 for
a medium sized bin, plus overhead.) In March, 9 months. The goal is to simplify
billing and ensure inactive bins/lockers don't accumulate by encouraging
annual cleanup. Any questions,contact Aubrey Martinez (aubreym@snf)

Thanks for your attention --

Your SNF Staff

--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
Paul G. Allen Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu

Preview of IEDM Presentations at Stanford: 9am-12pm on Dec. 7th, Fri @Packard 202

Preview of IEDM Presentations at Stanford

Date: December 7th, 2012 (Friday)
Time: 9am-12pm
Place: Packard 202
Host: Prof. H.-S. Philip Wong

1. 9:00 am

10.4 A Neuromorphic Visual System Using RRAM Synaptic Devices with Sub-pJ Energy and Tolerance to Variability: Experimental Characterization and Large-Scale Modeling,  S. Yu, B. Gao, Z. Fang***, H. Yu**, J. Kang*, H.-S. P. Wong, Stanford University, *Peking University, **South University of Science and Technology, ***A*STAR

We report metal oxide resistive switching memory (RRAM) as synaptic devices for a neuromorphic visual system. At the device level, we experimentally characterized the gradual resistance modulation of RRAM by hundreds of identical pulses and a low energy consumption (<1 pJ per spike). At the system level, we simulated the performance of image orientation selectivity on a neuromorphic visual system which consists of CMOS neuron circuits and a 16 kb RRAM array. It was found that the system can tolerate the variability which is commonly present in RRAM devices.

2. 9:30 am

20.5 Electrode/Oxide Interface Engineering by Inserting Single-Layer Graphene: Application for HfOx–Based Resistive Random Access Memory, H.-Y. Chen, H. Tian*, B. Gao, S. Yu, J. Liang, J. Kang***, Y. Zhang**, T.-L. Ren*, H.-S. P. Wong, Stanford University, *Tsinghua University, **Lawrence Berkeley National Laboratory, ***Peking University

In this paper, electrode/oxide interface with inserted single-layer graphene (SLG) is studied using Ramen spectroscopy and electrical measurement. Raman mapping and single point measurements show noticeable changes in both D-band and G-band signal of SLG during the electrical cycling. This might suggest a new methodology to investigate the migration of oxygen ions in metal oxide resistive random access memory (RRAM). Applying this interface engineering technique to HfOx-based RRAM, the SLG increases low resistance state (LRS) resistance (> 1MΩ) due to its intrinsically high out-of-plane resistance. This enables the reduction of RESET current by 22X and programming power consumption by 47X. This work indicates that interface engineering design plays an important role in addition to exploring different metal oxides or metal electrode materials for RRAM.

3. 10:00 am

14.6 State-of-the-art Graphene Transistors on Hexagonal Boron Nitride, High-k, and Polymeric Films for GHz Flexible Analog Nanoelectronics, J. Lee, K. Parrish, F. Chowdhury, T.-J. Ha, Y. Hao, L. Tao, A. Dodabalapur, R. Ruoff, D. Akinwande, University of Texas, Austin

We report state-of-the-art graphene transistors for flexible nanoelectronics with record current density, intrinsic gain, extrinsic frequency metrics, and the highest doubler conversion gain and power. In addition, current saturation, and robust electrical stability down to a record 0.7mm bending radius, and immersion in liquids were demonstrated for the first time.

4. 10:30 am

24.7 Exceeding Nernst Limit (59mV/pH): CMOS-Based pH Sensor for Autonomous Applications, K. Parizi, A. Yeh, A. Poon, H.S.P. Wong, Stanford University

A highly sensitive and accurate field-effect sensor was obtained in a standard differential pair CMOS structure without Ag/AgCl reference electrode. The device is composed of two sensors each with a floating gate (FG) field effect transistor (FET), a control gate (CG) and an extended sensing gate (SG). By extending the sensing gate and engineering the capacitance value of the CG, we achieved a remarkable sensitivity of 130mV/pH for our pH sensor exceeding the fundamental Nernst limit, 59mV/pH. In addition, we removed the bulky Ag/AgCl reference electrode by a novel technique employing differential measurement to cancel the effect of the common abnormal potential change occurs in the solution.

5. 11:00 am

26.1 Understanding Metal Oxide RRAM Current Overshoot and Reliability Using Kinetic Monte Carlo Simulation, S. Yu, X. Guan, H.-S.P. Wong, Stanford University

A Kinetic Monte Carlo simulator is developed for metal oxide resistive random access memory (RRAM) to study a full set of RRAM characteristics such as set/forming current overshoot, endurance, and retention. The simulations suggest that 1) eliminating the forming process and decreasing the parasitic capacitance is required for minimizing the overshoot effect and reducing the reset power consumption; 2) the degradation of endurance is mainly due to oxygen escaping from the electrode during cycling; 3) the oxygen migration barrier can be extracted from the retention baking test over a suitable temperature range.

6. 11:30

20.7 HfOx Based Vertical Resistive Random Access Memory for Cost-Effective 3D Cross-Point Architecture without Cell Selector, H.-Y. Chen, S. Yu, B. Gao, P. Huang*, J. Kang*, H.-S.P. Wong, Stanford University, *Peking University

Double-layer stacked HfOx vertical RRAM is demonstrated for 3D cross-point architecture using a cost-effective fabrication process. Electrode/oxide interface engineering using TiON layer results in non-linear I-V suitable for the selector-less array. The fabricated HfOx vertical RRAM shows excellent performances such as reset current (<50μA), switching speed (~50ns), switching endurance (>108 cycles), half-selected disturbance immunity (>109 cycles), retention (>105s @125oC). Moreover, a unique write/read scheme is proposed for 3D cross-point architecture, and the simulation shows that ~1Mb array without cell selector is achievable.

PhD Defense Announcement: Chia-Fang Chiang

Stanford University Ph.D. Oral Examination – Dept. of Mechanical Engineering

 

Title:

Micromachined Temperature Compensated Pressure Sensor
Implemented Using a Multi-Sensor Integration Platform

 

Speaker: Chia-Fang Chiang

Advisor: Professor Thomas W. Kenny

 

Date: Friday, December 14, 2012

Time: 10:00 am (refreshments at 9:45 am)

Location: Hartley conference center (Mitchell Earth Sciences) - Room 130

 

Abstract: 

 

Micromachined pressure sensors are widely used in our everyday lives: in automobiles they are implemented to monitor tire pressure and detect side crashes; in medical devices they are used to track blood pressure in the brain; and in navigation they are utilized to determine altitude and assist global positioning system (GPS) receivers. While the requirements for a pressure sensor vary depending upon the specific application, a common requirement is accurate sensing over a wide operating temperature range (-40 – 125 °C).

 

I will begin by introducing our capacitive pressure sensor design and demonstrating how it outperforms a piezoresistive pressure sensor with respect to temperature insensitivity. To further reduce temperature dependence, a high resolution resonant thermometer has been cofabricated with the capacitive pressure sensor, enabling the tracking of temperature fluctuations on the die and correction of the associated pressure error.

 

In the second half of the talk, I will discuss our development of a resonant pressure sensor. This is motivated by the emerging demand of altimeters which require high resolution (10Pa/meter). As the design is coupled to the die strain, the accuracy of the resonant pressure sensors is strongly influenced by errors induced by both temperature and package stress. We address this limitation with a multiple sensor solution where temperature and strain sensors are cofabricated to reduce the pressure sensor's temperature and package stress dependence, thus improving accuracy.

 

Throughout the talk, I will discuss the process flows enabling the fabrication of such structures. Key developments include time insensitive vapor etching of silicon dioxide with hydrofluoric acid to release structures as well as the fabrication of structures that can be driven and sensed in both in-plane (x,y) and out-of-plane (z) directions on either bulk silicon or SOI wafer substrates.

Re: GaAs etching in PQuest

hi Neil!

how's it be?! This guy sonny vo had a lot of amazing GaAs etches there. Just enable pquest, find a 'svo gaas etch' or anything with svo, load sample, hit run and you can say something like, 'i want my samples to turn into gold.' and after 45 minutes, you get your wish. Make sure to make eye contact with the machine when you say this. This is important. Active Pquest users know how emotional this machine can get. 

"Yusi Chen" <yusichen@stanford.edu>, a fellow Harris Group has been visiting the pawn shop regularly with his samples so connect with him.

$onny

On Tue, Dec 4, 2012 at 1:34 PM, Neil Dasgupta <dasgupta@stanford.edu> wrote:

Hi labmembers,

I am preparing a new process which involves etching features into GaAs.  I haven't worked much with GaAs in the past, and was hoping to benefit from the existing expertise.  I was planning to use P Quest, and was wondering if anybody has experience etching GaAs in this machine recently, and might be able to share recipes/etch rates (including selectivity for mask materials). I would like to etch on the order of 1 micron deep features.  Also, if you recommend any surface cleaning/pre-treatments before the etch, it would be greatly appreciated.

Thank you,
Neil Dasgupta
Prinz Group

--
Regards,
Sonny

----
Department of Applied physics, Stanford University
research group: http://snow.stanford.edu/index.html
626-216-4597

Which one shall I choose between Sirion and DB235 Dual-Beam?

Hi everyone,

 

I was wondering if anyone in this list is familiar with the SEMs in the SNL. I want to take some images of the fine structures on bacterial surface, which may need a resolution of at least 10 nm. I am planning to get trained on the SEMs in the SNL. It appears that before qualified to the training for FEI Magellan 400 XHR one has to be trained on either FEI Sirion SEM or the FEI DB235 Dual-Beam FIB/SEM. Could anyone make a suggestion that which one of the two is the better for my experiment with fixed bacteria? I hope to work on that one first and then consider whether to move on to Magellan. Thanks a lot!

 

Best,

 

Kangning

 

---

Kangning Ren, Ph.D.

Zarelab, Department of Chemistry

Stanford University

Tel: +1-650-723-8280

Email: kangning@stanford.edu

Lab website: http://www.stanford.edu/group/Zarelab/

GaAs etching in PQuest

Hi labmembers,

I am preparing a new process which involves etching features into GaAs. I haven't worked much with GaAs in the past, and was hoping to benefit from the existing expertise. I was planning to use P Quest, and was wondering if anybody has experience etching GaAs in this machine recently, and might be able to share recipes/etch rates (including selectivity for mask materials). I would like to etch on the order of 1 micron deep features. Also, if you recommend any surface cleaning/pre-treatments before the etch, it would be greatly appreciated.

Thank you,
Neil Dasgupta
Prinz Group

Important Badger Conversion Instructions

SNF Lab Members:

 

As most of you know SNF is in the process of converting from the Coral application to Badger Lab Management Software. Members will use Coral until the start of the holiday break and use Badger after the break. Reservations for after the break can be made in Badger with the usual reservation horizons. Many members already have Badger accounts and know that the look and feel of Badger is similar to Coral. New Badger users will have no trouble performing all of their normal functions. Our hope is to make this transition as simple as possible. It is; however, critical that all members read the information at the website below and move quickly to follow the instructions.

 

https://www.stanford.edu/group/snf/Badger/SNF-Conversion.html

 

Important Dates -

 

12-14   Final day to complete your application and verify your data in Coral and Badger.

12-21   Lab Closes – Coral use ends.

1-8       Lab Reopens – Badger is used over the break for reservations starting on the 8^th.

 

Regards,

 

The SNF Conversion Team

 

Re: Furnace on campus?

My sample  is ZrO2 ceramic. Need an annealing in ambient air, gold-contaminated, no outgassing.

Thanks

Jihwan

On Tue, Dec 4, 2012 at 10:45 AM, JIHWAN AN <jihwanan@stanford.edu> wrote:

Hi all,

I'm Jihwan in Prinz group. I am looking for a furnace which can go up to ~1500C on campus. Anybody know where I can find it?

Thanks,

Jihwan

--
Jihwan An
Ph.D. Candidate
Nanoscale Prototyping Laboratory (NPL)
Department of Mechanical Engineering
Stanford University, CA

cell : 650-862-0414
e-mail: jihwanan@stanford.edu

--
Jihwan An
Ph.D. Candidate
Nanoscale Prototyping Laboratory (NPL)
Department of Mechanical Engineering
Stanford University, CA

cell : 650-862-0414
e-mail: jihwanan@stanford.edu

Mentors and Projects needed for SNF/NNIN Research Experience for Undergraduates (REU) program

SNF Labmembers,
      We’re soliciting projects and mentors for the SNF/NNIN Research Experience for Undergraduates (REU) program for next summer.  For this program, NSF provides funds for non-Stanford undergraduate students to work during the summer with Stanford graduate students on projects which utilize the Stanford Nanofabrication Facility.  The objective is to give a select group of undergraduates from across the country an experience in graduate-level research.
        In this program the student assists the graduate student for the summer by doing lab work, primarily in SNF, and analyzing results that are useful for the graduate student's Ph.D. research.  The idea is that the undergraduate would have a more-or-less complete project to report on at the end, but at the same time doing something that benefits your own research.  At the end of the summer, the student joins the other NNIN REU students doing work at the other 13 NNIN universities to report on their work and experiences.

        The graduate student mentor should be an SNF labmember (or at least have someone who is a labmember able to help with the student and project), and have at least some part of the research involve SNF.
         Along with doing a project, the student would join your research group for the summer, attending meetings, seminars and any other group activities.  In addition, I lead weekly meetings for the 6 SNF REU students to teach them about nanotechnology, giving technical presentations and writing scientific papers, as well as helping with any logistical issues.  And SNF helps with training the students at the beginning of the program.   The program pays the for the students travel expenses to/from Stanford, housing for the summer, a stipend, and $5,000 for SNF/SNL lab fees.  
        Besides having an undergraduate working with you on your research for the summer, you would also be able to experience the satisfaction of mentoring a young student, probably from a school that doesn’t have the research facilities and opportunities of Stanford.  Hopefully by the end of the program the student will have a much better idea of what graduate research and life is all about.  And whether you plan yourself to go onto either an academic or industrial career, this program  should give you a good experience in mentoring and guiding a younger person.
       If you are interested in being a mentor, talk to your faculty advisor about this, and then contact me with a proposed research topic. (I will be asking for a short proposed project description soon).   For a list of  previous years’ students, mentors, and projects, go to http://snf.stanford.edu/education/undergraduate.htm        (You don’t have to be so specific right now with your  project title - just a general idea of what the project is about and what the student might do.  And don’t make the projects too ambitious.)   We will be funding 6 projects, which we will decide upon in the next few weeks.
        If you are a faculty, and want an SNF REU student in your group, let me know and send me the same type of information about a possible project.
      
Thanks, and I hope to hear from you.
                        -Mike Deal, Sr. Research Scientist and SNF Director of Special Programs.

Re: Furnace on campus?

how big of a sample do you have, what cleanliness is it, and what gases/pressure do you need the ambient to be?

j

On Tue, Dec 4, 2012 at 10:45 AM, JIHWAN AN <jihwanan@stanford.edu> wrote:

Hi all,

I'm Jihwan in Prinz group. I am looking for a furnace which can go up to ~1500C on campus. Anybody know where I can find it?

Thanks,

Jihwan

--
Jihwan An
Ph.D. Candidate
Nanoscale Prototyping Laboratory (NPL)
Department of Mechanical Engineering
Stanford University, CA

cell : 650-862-0414
e-mail: jihwanan@stanford.edu

Furnace on campus?

Hi all,

I'm Jihwan in Prinz group. I am looking for a furnace which can go up to ~1500C on campus. Anybody know where I can find it?

Thanks,

Jihwan

--
Jihwan An
Ph.D. Candidate
Nanoscale Prototyping Laboratory (NPL)
Department of Mechanical Engineering
Stanford University, CA

cell : 650-862-0414
e-mail: jihwanan@stanford.edu

Seminar on "Light-Emitting Diodes for Illumination Applications"

Light-Emitting Diodes for Illumination Applications


Mike Krames (CTO, Soraa)
4:15pm, Dec 3 (Monday)
Location: Paul Allen Building (CIS)-101X

Abstract -

Light-Emitting Diode (LED) technology advancements accelerated with the introduction of GaN-based blue- and white-emitting LEDs in the 1990s and have ushered in an era of new lighting products with unprecedented luminous efficacy and the potential for substantial savings in worldwide electricity consumption. However, the very high prices associated with these new products are limiting the adoption rate and threaten to substantially reduce and/or delay the positive impact that is promised by solid state lighting. A primary reason for the high costs are the performance limitations and complicated semiconductor processing operations inherent to the utilization of foreign substrates as the materials platforms for most of today's GaN-based LEDs. In contrast, recent advancements in GaN substrate technology have provided an opportunity for products platforms based on the native substrate. This technology platform, GaN-on-GaN(tm), opens the path to new operating regimes and simplified LED architectures which enable unprecedented performance and revolutionary designs for solid-state lighting products. First generation products based on GaN-on-GaN(tm) will be described.


Speaker Bio -

Mike Krames received his Ph.D. degree in electrical engineering from the University of Illinois at Urbana-Champaign, IL, in 1995, under the supervision of Prof. Nick Holonyak, Jr. After graduation, he joined Hewlett-Packard Optoelectronics Division as a research engineer developing high-power visible-spectrum LEDs. He subsequently formed and ran the Advanced Laboratories for Lumileds Lighting Co., and later Philips Lumileds, in San Jose, CA. There his research focused on advanced III-nitride epitaxy, LED device technology, and luminescent materials for photon down-conversion.

Mike was involved in spearheading several technology advancements at Lumileds, including flip-chip technology (the basis for Luxeon(tm)), thin-film technology, photonic crystal LEDs, ceramic phosphors, and advancing understanding behind the "droop" mechanism in InGaN-GaN LEDs. In 2009, Mike joined the management team of Soraa as Chief Technology Officer. Mike is a senior member of IEEE and has published more than 75 papers and been granted more than 80 U.S. patents in the field of solid-state lighting and displays.

re:Badger Questions and Concerns for industrial users

Pradeep,

As a current user of Badger I’m sure you’ve been relieved to see that much of the look and feel of the application is identical to that of Coral and that there are a number of enhancements that benefit members and staff alike. In addition to the presentations a couple of months ago, more information on the conversion specifics will be available shortly. Rest assured that every effort is being made to make the transition as painless as possible.

It is true that Badger, like so many software resources at Stanford and elsewhere, restricts offsite access. Stanford does supply a VPN client that enables offsite use of the application in most cases. I understand that your employer has a particularly restrictive policy concerning this. I can certainly appreciate their concerns for the security of mission critical resources and would only add that, firewalls, data encryption and increasingly complex authentication strategies are a sometimes annoying, but inevitable consequence of the need for data and application security in the face of sophisticated threats. I have used the Stanford VPN successfully for years and have found it to be robust and reliable. I’m hopeful that most members, like myself, will find that offsite access from home, work or the local café will not be an issue.  

The good news on multiple accounts is that Badger can support functionality identical to that of Coral. We will have more information on this and other issues in the very near future.  Again, we are committed to making the conversion to Badger as seamless as possible and expect most members to find that the conversion will make the scheduling and use of equipment in Stanford’s shared labs more convenient.

Regards,

Michael Bell

 

Steam back on …

SNF lab members and Allen Building occupants:

As of about 1:30 today steam service to the building has been restored and Jose Solorzano has done a thorough check of all affected systems and found them to be functioning properly.

In particular, temperature and humidity control in the clean room has been restored to normal levels. Other utilities such as domestic hot water should also be ready for use.

Thanks to the steam shop and to Jose for getting this repair done and systems brought back on line sooner than expected. To my knowledge all SNF operations can resume as normal.

Have a good weekend,

John

Sent from my iPhone