TODAY - Stanford Optical Society BBQ, 4pm, outside McCullough

Join Stanford Optical Society for a BBQ today!

-

Re: Vendor for TEOS and CMP

Thank you, Lidia!

I've received some replies of local vendors and I will start from there. I appreciate you're help!

-P

On Jun 27, 2011, at 11:48 AM, Lidia Vereen wrote:

> Entrepix
>
> -----Original Message-----
> From: Patrick Wilhite [mailto:pwilhite@scu.edu]
> Sent: Sunday, June 26, 2011 10:46 PM
> To: labmembers@snf.stanford.edu
> Subject: Vendor for TEOS and CMP
>
> Dear Lab Members,
>
> Would any of you know of nearby companies that can perform TEOS SiO2 filling
> and/or CMP services?
>
> Thanks,
>
> -Patrick
>
>

RE: Vendor for TEOS and CMP

Entrepix

-----Original Message-----
From: Patrick Wilhite [mailto:pwilhite@scu.edu]
Sent: Sunday, June 26, 2011 10:46 PM
To: labmembers@snf.stanford.edu
Subject: Vendor for TEOS and CMP

Dear Lab Members,

Would any of you know of nearby companies that can perform TEOS SiO2 filling
and/or CMP services?

Thanks,

-Patrick

Process Clinic today (Monday) 2-3 pm

Greetings all --

Just a reminder of today's process clinic, from 2-3 pm, in the cubicle
area outside Maureen's office. Bring process questions and mask
layouts. Staff and senior labmembers will be on hand to brainstorm ideas.

Your SNF staff

--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
Paul G. Allen Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu

Vendor for TEOS and CMP

Dear Lab Members,

Would any of you know of nearby companies that can perform TEOS SiO2 filling and/or CMP services?

Thanks,

-Patrick

Water leak cleaned up

Hi all --

Things are OK now. There was a process cooling water line on an oven
that developed a leak, but Jim isolated it and most of the water is now
cleaned up. The leak was substantial, but small enough that the process
cooling loop seems to have been unaffected. Thanks for everyone's help!

Your SNF staff

--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
Paul G. Allen Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu

water leak behind the 90C oven in the litho area

Jim is cleaning the area.

Questions about negative PR for photolithography

Hi all,

I'd like to use a negative PR for photolithography at SNF.
But, I cannot find proper information about it from labmembers' wiki.
If you know which negative PR is allowed at SNF, please let me know it.
Thanks.

Pil Sung Jo

Ph.D. Candidate
Salleo Research Group
Department of Materials Science & Engineering
Stanford University
Phone : 650-739-3374
E-mail : chovic99@stanford.edu

Proposal to retire the SEMHITACHI -- Hitachi S-800 Cold Emission Scanning Electron Microscope system at SNF. Seeking destinations to donate this system to...

Greetings SEMHITACHI User and SNF Lab Members:

The Hitachi S-800 Scanning Electron Microscope system is widely
considered to be the 'Chevy II Nova of SEMs' with many thousands of
these systems sold in the United States by Hitachi Instruments.
They are simple to use, robust in their design, and very flexible in
their operations across many scientific applications. Through the
course of the last decade working in the SNF Ebeam Lab, I have trained
hundreds of Users conducting the 'SEM Practicum' classes on this tool.
It offers minimum resolution to ~10 to 12 nm across a range of
acceleration voltages from 500 volts to 25 keV and handles samples as
large as 100 mm diameter. On smaller samples that can be loaded through
the load lock it also is an excellent system for cross section analysis.

Now that several other capable SEM and EBL writing and measurement
systems are available to Users working at SNF, and our other sister
laboratories at Stanford, we have seen a decided drop off in usage of
this tool and the income it generates through the course of the last
years time. Now in order to make space for the new maintenance area to
be constructed in the SEMHITACHI lab area, I have decided to retire this
tool and remove it from the SNF Ebeam lab tool suite this summer.

I am seeking a new destination for this tool preferably a college,
school, or research group whom wishes to take this tool in hopes that it
may be useful to another group for their research and continue its use
as a training tool for new technicians and engineers moving into the future.

Please contact me directly during my office hours or by email if you are
interested in obtaining this tool as a donation. My office hours are
Tuesday to Friday 9:00 - 10:00 AM at ALLEN 31 or by email.

Thank you for your support!

James Conway

Stanford Optical Society Summer BBQ!!

OSA Summer BBQ!!

Proposal to retire the Hitachi HL-700F Ebeam Writer. Speak up now or hold your peace ...

Greetings Users of the Hitachi HL-700F and the great SNF Community:

The Hitachi HL-700F Electron Beam Writer has been here at SNF for many years with a sorted history of up time despite significant efforts made to keep it in operational specification.
In early 2010, after a decided effort by Ted Berg, Hitachi Field Service and myself, we were able to once again bring this tool into operational service and within specifications for performance.
This 30 keV EBL system, writing in 2 mm square field size at 100 MHz speed is capable of writing isolated line features to less than 50 nm and gaps to less than 30 nm with write field and overlay stitching accuracy to within  less than 150 nm (mean + 3 sigma). In the past this tool has serviced hundreds of EBL jobs and SNF projects, but with a challenging level of expertise required of the operator, due to its aged computer control interface (VAX VMS) and its general sensitivity to operator mistakes using the command line which often brought the system down for extended periods of time in the past.

In 2010 during its last period of extended up time we had a remarkably successful period of writing on this system with several projects brought in and completed on the tool, many other groups trying out the tool for evaluation for their project needs at no charge, and last but not least hundreds of Waveguides and Gratings, Nano Imprint Lithography Molds, and Process Control Monitor test patterns written to aid in EBL process development in my work here at SNF.  There was also some interest from industrial and SU projects working in solar and other 2-D gratings patterns too.  The system maintained sub-50 nm lines and for most writes stitching was well within its specifications.  These efforts resulted in many tens of centimeters square patterned onto silicon and quartz being successfully writing by the system with good quality.
However none of the outside clients committed to using the tool in earnest for their projects, mainly due to not having their own skilled operators on that system.  In one case the group ran out of funds for their project before we could get their custom samples onto the system to write last summer.

In late November 2010 we encountered the loss of several subsystems on the tool after an unusual voltage transient came through the house mains which effected the VAX emulation card functionality, latches in the switching sections in the MD and SD imaging section, and finally loss of the FE-Gun controls and ultimately the loss of emission in the FE-Gun on the system.  The final event that resulted in the system being shut down all of this year thus far was the loss of the custom wired Helix cryo-compressor at the January 2011 start up phase.

Due to very limited resources available to the Ebeam Lab in 2011 I have not been able to get the resources to bring this system back up into normal operation, nor to further troubleshoot the sub-systems brought down last November.

This email is to inform you that unless you speak up now and offer us the monies and support we require to bring the system back up that we will desire to retire the HL-700F and will remove the system from the Ebeam Lab at Stanford Nanofabrication Facility by the end of the summer.   This will allow Ted Berg and myself to focus our attention on other EBL and Novel Lithography methods without the significant burden that this system has placed on resources here at SNF in the past.

Your comments are invited, please reply to ebeam@snf.stanford.edu


Thank you for your support!


James Conway
Ted Berg
Ebeam Technology Group



               
40 nm Isolated line in HSQ at the threshold of cross link this material           



Isolated 28 nm Dot shot exposure in HSQ slightly over-dosed.

Re: Problem epi2 SNF 2011-06-20 11:05:59: OK TO RUN NOW? TGO done?

Testing is done gas is back on. Thanks for your patience. Ted

Yes its done
On 6/20/2011 11:05 AM, gyama@snf.stanford.edu wrote:

Reminder : EE PhD Oral Examination - Jie Zhang, Today, 2:00 PM

Title : Variation-Aware Design of Carbon Nanotube VLSI Circuits
Speaker : Jie (Jerry) Zhang
Advisor : Prof. Subhasish Mitra
Date : June 20, 2011
Time : 2:00 pm (refreshments at 1:45 pm)
Location : CIS-X Auditorium

Abstract
Carbon Nanotube Field Effect Transistors (CNFETs) are excellent candidates for building highly energy-efficient future electronic systems. Variations specific to carbon nanotubes (CNTs) pose major obstacles to energy-efficient and robust CNFET digital VLSI. CNFET circuits can suffer from large performance variations, reduced yield, and increased susceptibility to noise. CNT processing techniques alone are inadequate to overcome these challenges.

We present an integrated approach, combining CNFET modeling, processing and circuit design, to create VLSI circuits tolerant to CNT variations. Probabilistic models, calibrated using experimental data, are used to analyze the effects of two major sources of CNT variations: metallic CNTs (CNTs with no / very small bandgaps) and CNT density variations (due to the non-uniformity in CNT positioning).

Using these models, we create a probabilistic framework to derive simple yet useful CNFET processing and circuit design guidelines to overcome CNT variations. The effectiveness of this approach is demonstrated using two examples:

1. CNT variations result in functional failures of CNFET circuits. The failure probability may be reduced through CNFET sizing but at substantial energy costs. A new layout design technique, which engineers correlation among various CNFETs, reduces CNFET circuit failure probability at significantly lower costs.

2. We quantify the impact of CNT variations on delay variations of CNFET circuits. We explore the space of CNFET sizing, together with various possibilities to improve CNFET processing, to minimize circuit delay variations at low energy costs.

Fwd: FIJI inspection today

-------- Original Message --------

Subject:	FIJI inspection today
Date:	Mon, 20 Jun 2011 06:00:59 -0700
From:	Ted Berg <tberg@stanford.edu>
To:	cis-building@cis.stanford.edu

Hello All ,     Just a reminder that we have our inspection for the FIJI ALD today so. Hello All,     As part of the permit inspection process for FIJI, we will be  testing some of the sensors in CIS and CISX Monday morning from 9:00 am  for about 2 hours. Please disregard all alarms during that time period.  Horns and strobes may activate. Sorry for any inconvenience. Thanks for  your patience. Ted 

Re: Comment p5000etch SNF 2011-06-04 12:43:11: wand and Ch. B chuck not very clean

Found the chamber and the wand were clean. Ran wafers with no problems.

Re: Problem p5000etch SNF 2011-06-15 16:26:40: wafer lost in chamber C

Recovered the wafer and cleaned the chamber. Cycled 8 wafers with no problems.

Re: Problem p5000etch SNF 2011-06-15 15:21:59: CH B offliine

Placed the chamber online.

Problem p5000etch SNF 2011-06-15 16:26:40: wafer lost in chamber C

Vacuum service offline for Chamber C.

Problem p5000etch SNF 2011-06-15 15:21:59: CH B offliine

Turbo is off.

Leftover Food in Allen Building Kitchen

Leftover Panda Express in the kitchen.  Enjoy :-)

Re: Comment p5000etch SNF 2011-06-09 03:57:46: I could extract my wafer

Re: Problem p5000etch SNF 2011-06-09 03:00:24: problem for unloading wafer

Comment p5000etch SNF 2011-06-09 03:57:46: I could extract my wafer

and process finished normally. That was due to my easy mistake, and the instrument is normally working. Sorry for bothering you

Problem p5000etch SNF 2011-06-09 03:00:24: problem for unloading wafer

My one wafer is still inside the chamber and I could not extract it by myself. Sorry for the inconvinience.

Reminder : EE PhD Oral Examination - Jenny Hu, Wednesday, June 8, 10:00 AM

Stanford University PhD Oral Defense - Department of Electrical Engineering

Title:  Metal/III-V Effective Barrier Height Tuning
Speaker: Jenny Hu 
Advisor: Professor H.-S. Philip Wong

Date: June 8, 2011 (Wednesday)
Time: 10:00 AM (Refreshments served at 9:45 AM)
Location: Paul Allen Auditorium (CISX-AUD)

 

Abstract:

As silicon CMOS technology reaches its fundamental scaling limits, alternative materials such as high mobility III-V compounds have proven to be strong contenders for extending high performance logic. However, most promising demonstrations of III-V FET/HEMTs have micron-scale source/drain spacing despite gate lengths on the nanometer scale. III-V semiconductor devices have historically relied on alloyed ohmic contacts which require large spacings to prevent shorting between the source and drain after alloying, where contacts can diffuse up to hundreds of nanometers.  This severely limits the scalability of III-V logic technology. Non-alloyed contacts offer a practical route to greatly reduce the III-V device footprint for application in future technology nodes.

In this talk, I demonstrate a route to non-alloyed contacts by shifting the pinned III-V Fermi level to reduce the metal/n-GaAs and metal/n-InGaAs Schottky barrier heights.  The Fermi level is controlled by the insertion of thin dielectrics in a metal-insulator-semiconductor (MIS) contact structure. The MIS contact is studied across a wide range of metal and dielectric materials, and found to have great flexibility in the material selection. I will also discuss the use of bi-layer high-κ dielectrics, and report results which show that despite an overall thicker dielectric, there is an additional reduction in the barrier height and contact resistance beyond that of a single dielectric MIS.  This MIS contact is then integrated in an InGaAs MOSFET as a non-alloyed source/drain contact, though it can also be applied to Schottky Barrier FETs. I will conclude by discussing possible physical mechanisms of the observed barrier height reductions, by examining the effects of fixed charge and electronic dipoles. 

Reminder: MSE PhD Oral Examination: Yi Wei Chen (Wednesday, June 8th @ 3:15 PM in Packard 101)

University PhD Dissertation Defense

Atomic Layer Deposited Metal Oxides for Semiconductors Used in Aqueous Solutions

(Vincent) Yi Wei Chen

Department of Materials Science and Engineering

Advisor: Prof. Paul C. McIntyre

When: Wednesday, June 8th 2011, 03:15 pm (Refreshments at 3:00 pm)
Where: Packard 101
http://campus-map.stanford.edu/index.cfm?ID=04-030

 

            In recent years, atomic layer deposition (ALD) has become a popular technique to deposit ultra-thin films with superior conformality and thickness control. Because of its unique surface adsorption-limited mechanism and the resulting capability of deposition at low temperatures and moderate pressures, ALD has found industrial applications in field effect transistor fabrication and coating of multilayer interconnection metallization.  In this work, I have explored the potential of ALD-grown metal oxide layers in applications beyond typical electronics technologies. In particular, this research has focused on using ALD-grown metal oxides to enhance the performance and stability in aqueous solutions of biomolecular sensors and semiconducting anodes for photoelectrochemical fuel synthesis.

            In the biosensing application, we have replaced the SiO₂ gate dielectric material typically used in high sensitivity bio-field-effect-transistors (bioFET) with high dielectric constant HfO₂. The SiO₂ bioFET gate dielectric suffers from poor stability and non-ideal dielectric response at the very small physical thicknesses required to achieve high sensitivity. ALD-grown HfO₂, on the other hand, is capable of providing high capacitance density with a physically thicker dielectric layer, thanks to its large dielectric constant. With the ALD-HfO₂ gate dielectric, biosensor switching behavior was demonstrated using capacitance-voltage measurements in water, while at the same time maintaining the desired high capacitance. In addition, we have verified bio-functionalization of the HfO₂ film surface with biotin molecules via photoelectron spectroscopy, and detected streptavidin and avidin binding with capacitance-voltage analysis and molecular AFM imaging methods respectively.

            For the solar fuel synthesis, we have studied the behavior of ALD-TiO₂ tunnel oxides that can protect heretofore unstable semiconductors, such as Si, used as photoanodes in water splitting. For several decades, intense research effort has been devoted to identifying an efficient photoelectrochemical cell for oxidizing water under solar illumination.   The resulting hydrogen and oxygen can be used to store energy from the intermittent terrestrial solar resource renewably, using water as a feedstock. However, photoanode materials choices have always been limited because the water oxidation half reaction at the anode surface is highly corrosive and requires large overpotentials. As a result, only oxidation-stable wide bandgap semiconductors such as TiO₂ and Fe₂O₃ have been used as the photoanode.  These photoanodes exhibit poor efficiency, however, because of their large bandgaps. Lower bandgap semiconductors, such as Si, are capable of absorbing solar light much more efficiently, but are easily corroded during water oxidation. In this work, a silicon photoanode was passivated by a thin and pinhole-free layer of ALD-TiO₂ such that efficient light absorption in the Si and the chemical stability of the TiO₂ can be exploited at the same time. This ALD-grown nanocomposite photoanode has been demonstrated to perform water oxidation with low overpotentials, while at the same time maintaining good stability with hours of continuous operation. The tunneling of electronic carriers through the thin ALD-TiO₂, required to sustain high oxidation rates, has also been investigated by varying the TiO₂ thickness.

Reminder: Seminar-Tomorrow-Packard 202-Nanobridge Technology

Nanobridge Technology

Dr. Munehiro Tada

Wednesday, June 8th, 2011, 2 pm
Place: Packard 202

Abstract:

Scaling of CMOS devices and interconnects has contributed to high performance and low power operation of ULSI devices. Due to excessive stand-by power accompanying device shrinking, further scaling is experiencing serious roadblocks, and in near future, scaling will certainly face a physical limit of the device dimension. One of the solutions to enhance device performance while keeping the power consumption low is to introduce BEOL devices such as memory, transistor and switch, which are integrated in the interconnect layers without increasing the chip-size. For BEOL devices, a nonvolatile solid-electrolyte switch, NanoBridge (NB) is used. The NB is a switch consisting of a solid-electrolyte sandwiched between an active electrode (Cu) and an inert electrode (Ru). The operation power and stand-by power consumption of a programmable logic device can be greatly improved by using NB-based crossbar switches instead of conventional SRAM-based switches.
In this talk, we propose the embedding of NanoBridge (eNB) structure in Cu interconnects coupled with the thin solid-electrolyte, where the Cu interconnect itself works as a source of bridging ions. We newly developed a forming-free polymer solid-electrolyte (PSE) switch. The switching time and its variations are investigated. An ALU-type programmable unit cell, a 32x32 crossbar switch and a 1k re-programmable cell array are subjected to a practical of the nonvolatile PLD under a 90-nm CMOS. The fundamental operation of the circuit and dynamic power are demonstrated comparing with those of a standard SRAM- based design.

Biography:

Munehiro Tada received the Ph.D. degree from Keio University in Yokohama, Japan. He joined NEC Corporation, Kanagawa, Japan, in 1999, where he was engaged in the development of ULSI process and device, especially for low-power application specified integrated circuits (ASICs). From 2007 to 2008, he was a visiting researcher at Stanford University, Stanford, CA, for research of germanium transistor and three-dimensional ICs. Currently he is a principal researcher with the Green Innovation Research Laboratories in NEC Corporation, and involved in device technologies for embedding memory and switch devices into the logic devices. His current research interests include nonvolatile resistive switch, memory, multilevel interconnect, and three dimensional ICs for low power and high-performance logic applications.
Dr. Tada is a senior member of the IEEE Electron Devices Society and the Japan Society of Applied Physics. He is a recipient of the 72nd Exhortation Award from the Chemical Society of Japan in 1997.

Reminder: EE PhD Oral Examination - Yoonyoung Chung, Tuesday, June 7, 3:30 PM

Stanford University Oral Defense - Department of Electrical Engineering

Speaker: Yoonyoung Chung
Principal Advisor: Prof. Zhenan Bao
Co-advisors: Prof. Boris Murmann and Prof. Yoshio Nishi

Date: Tuesday, June 7, 2011
Time: 3:30 PM (Refreshments at 3:15 PM)
Location: Packard 101

Title: Organic Transistors for Flexible Electronics: fabrication and device physics

Abstract:
Organic transistors have shown promising potentials in flexible electronics. Because the transistors can be directly fabricated on flexible plastic substrates at low temperatures less than 100 °C, researchers envision development of novel electronic applications, such as flexible displays, flexible circuits, and conformal sensors. However, there are still several challenges to be solved for making practical applications, beyond laboratory-level demonstrations.

In the first part of my talk, I will present fabrication technologies for organic transistors. I have demonstrated high-capacitance gate dielectric on plastic substrates using atomic layer deposition. This low-temperature process was used to fabricate high-performance flexible organic transistors. Also, I will describe flexible shadow masks made of parylene-C for making small patterns. Due to their good adhesion on a variety of surfaces, the shadow masks patterned small feature sizes of less than 10 μm with high yield.

Second, I will present controlling current-voltage characteristics of organic transistors from the device physics point of view. Self-assembled monolayers and different gate electrodes were used to modify electric dipoles in the gate dielectric and gate work functions, respectively. Engineering the dipoles and the gate work functions provided a wide range of threshold voltage control over 0.6 V at a supply voltage of 2.5 V. I will also show that the dipoles can be used to improve significantly the air stability of n-channel (electron conducting) organic transistors, which are generally not stable in air.

Reminder: MSE PhD Oral Examination: Shu Hu (Monday, June 6th @ 10:00 AM in Clark Auditorium)

University PhD Dissertation Defense

Nanoscale Germanium Crystal Growth and Epitaxy Control for Advanced Electronics and Solar Cells

Shu Hu
Department of Materials Science and Engineering

Advisor: Prof. Paul C. McIntyre
When: Monday, June 6th 2011, 10:00 am (Refreshments at 9:45 am)
Where: James H. Clark Center Auditorium
http://campus-map.stanford.edu/index.cfm?ID=07-340

    Semiconductor crystal growth at the nanoscale and integration of different materials systems are central themes of materials research. They enable novel materials processes and device applications, and may shape the landscape of future technologies. A major challenge is growth of high-quality single crystal semiconductors (e.g. Ge) on large-mismatch (e.g. Si) and non-crystalline (e.g. glass) substrates, while managing the thermal constraints of the underlying substrates. As-grown vertical semiconductor nanowires have been demonstrated as sensors, and nanoelectronic and nanophotonic devices. However, little attention has been paid to their unique structural properties: vertical Ge nanowires can be epitaxially grown on (111)-oriented Ge and Si substrates. In my talk, I will focus on nanowire-seeded crystallization and metal-induced crystallization to realize three-dimensional integration and nanostructured solar cells. Fundamental aspects of crystal growth at the nanoscale will be discussed.

Three-dimensional (3-D) device stacking and heterogeneous materials integration can improve the performance and functionality of Si-based electronics. First, I will demonstrate liquid phase epitaxy seeded by Ge nanowires to grow micron-sized single crystal Ge islands on SiO₂. Vertical Ge nanowires can transfer the orientation and perfection of the underlying Si lattice to overlying layers several microns above. Liquid phase epitaxy was found to eliminate random nucleation that competes with epitaxial growth from nanowire seeds. The structure and electronic properties of Ge islands will be discussed. Given a low thermal budget annealing process, this technique can be repeated to build multiple active device layers, a key requirement for the fabrication of densely interconnected 3-D integrated circuits.

Vertical, tapered Ge nanowire arrays have shown enhanced light absorption properties, promising for high-efficiency solar cells. Metal-induced crystallization is a low-temperature crystal growth process for polycrystalline semiconductor deposition on large-area, non-crystalline substrates. Then, I will demonstrate Al-induced layer exchange crystallization to form polycrystalline Ge thin films with micron-sized grains and (111)-preferred orientation at 200°C. The textured thin films can serve as growth templates for aligned nanowire arrays. Imaging nucleation, growth and coalescence of Ge crystal islands allows us to characterize, model and control Ge crystallization kinetics, by tuning the knobs such as nucleation density.

--

Shu Hu, PhD Candidate

Department of Materials Science and Engineering

Stanford University

476 Lomita Mall, Stanford, CA 94305-4045

Comment p5000etch SNF 2011-06-04 12:43:11: wand and Ch. B chuck not very clean

was performing a backside strip of my wafers and now the front side (which was face down for the etch) has clear marks from the chuck and the vacuum wand location. residue did not come off using an O2 plasma.

Correction: Seminar-Nanobridge Technology

Mark your calendars!

Nanobridge Technology

Dr. Munehiro Tada

Wednesday, June 8th, 2011, 2 pm
Place: To be announced soon!

Abstract:

Scaling of CMOS devices and interconnects has contributed to high performance and low power operation of ULSI devices. Due to excessive stand-by power accompanying device shrinking, further scaling is experiencing serious roadblocks, and in near future, scaling will certainly face a physical limit of the device dimension. One of the solutions to enhance device performance while keeping the power consumption low is to introduce BEOL devices such as memory, transistor and switch, which are integrated in the interconnect layers without increasing the chip-size. For BEOL devices, a nonvolatile solid-electrolyte switch, NanoBridge (NB) is used. The NB is a switch consisting of a solid-electrolyte sandwiched between an active electrode (Cu) and an inert electrode (Ru). The operation power and stand-by power consumption of a programmable logic device can be greatly improved by using NB-based crossbar switches instead of conventional SRAM-based switches.
In this talk, we propose the embedding of NanoBridge (eNB) structure in Cu interconnects coupled with the thin solid-electrolyte, where the Cu interconnect itself works as a source of bridging ions. We newly developed a forming-free polymer solid-electrolyte (PSE) switch. The switching time and its variations are investigated. An ALU-type programmable unit cell, a 32x32 crossbar switch and a 1k re-programmable cell array are subjected to a practical of the nonvolatile PLD under a 90-nm CMOS. The fundamental operation of the circuit and dynamic power are demonstrated comparing with those of a standard SRAM- based design.

Biography:

Munehiro Tada received the Ph.D. degree from Keio University in Yokohama, Japan. He joined NEC Corporation, Kanagawa, Japan, in 1999, where he was engaged in the development of ULSI process and device, especially for low-power application specified integrated circuits (ASICs). From 2007 to 2008, he was a visiting researcher at Stanford University, Stanford, CA, for research of germanium transistor and three-dimensional ICs. Currently he is a principal researcher with the Green Innovation Research Laboratories in NEC Corporation, and involved in device technologies for embedding memory and switch devices into the logic devices. His current research interests include nonvolatile resistive switch, memory, multilevel interconnect, and three dimensional ICs for low power and high-performance logic applications.
Dr. Tada is a senior member of the IEEE Electron Devices Society and the Japan Society of Applied Physics. He is a recipient of the 72nd Exhortation Award from the Chemical Society of Japan in 1997.

Seminar-Nanobridge Technology

Nanobridge Technology

Dr. Munehiro Tada

March 8th, 2011, 2 pm
Place: To be announced soon!

Abstract:

Scaling of CMOS devices and interconnects has contributed to high performance and low power operation of ULSI devices. Due to excessive stand-by power accompanying device shrinking, further scaling is experiencing serious roadblocks, and in near future, scaling will certainly face a physical limit of the device dimension. One of the solutions to enhance device performance while keeping the power consumption low is to introduce BEOL devices such as memory, transistor and switch, which are integrated in the interconnect layers without increasing the chip-size. For BEOL devices, a nonvolatile solid-electrolyte switch, NanoBridge (NB) is used. The NB is a switch consisting of a solid-electrolyte sandwiched between an active electrode (Cu) and an inert electrode (Ru). The operation power and stand-by power consumption of a programmable logic device can be greatly improved by using NB-based crossbar switches instead of conventional SRAM-based switches.
In this talk, we propose the embedding of NanoBridge (eNB) structure in Cu interconnects coupled with the thin solid-electrolyte, where the Cu interconnect itself works as a source of bridging ions. We newly developed a forming-free polymer solid-electrolyte (PSE) switch. The switching time and its variations are investigated. An ALU-type programmable unit cell, a 32x32 crossbar switch and a 1k re-programmable cell array are subjected to a practical of the nonvolatile PLD under a 90-nm CMOS. The fundamental operation of the circuit and dynamic power are demonstrated comparing with those of a standard SRAM- based design.

Biography:

Munehiro Tada received the Ph.D. degree from Keio University in Yokohama, Japan. He joined NEC Corporation, Kanagawa, Japan, in 1999, where he was engaged in the development of ULSI process and device, especially for low-power application specified integrated circuits (ASICs). From 2007 to 2008, he was a visiting researcher at Stanford University, Stanford, CA, for research of germanium transistor and three-dimensional ICs. Currently he is a principal researcher with the Green Innovation Research Laboratories in NEC Corporation, and involved in device technologies for embedding memory and switch devices into the logic devices. His current research interests include nonvolatile resistive switch, memory, multilevel interconnect, and three dimensional ICs for low power and high-performance logic applications.
Dr. Tada is a senior member of the IEEE Electron Devices Society and the Japan Society of Applied Physics. He is a recipient of the 72nd Exhortation Award from the Chemical Society of Japan in 1997.

EE PhD Oral Examination - Jenny Hu, Wednesday, June 8, 10:00 AM

Stanford University PhD Oral Defense - Department of Electrical Engineering

Title:  Metal/III-V Effective Barrier Height Tuning
Speaker: Jenny Hu 
Advisor: Professor H.-S. Philip Wong

Date: June 8, 2011 (Wednesday)
Time: 10:00 AM (Refreshments served at 9:45 AM)
Location: Paul Allen Auditorium (CISX-AUD)

 

Abstract:

As silicon CMOS technology reaches its fundamental scaling limits, alternative materials such as high mobility III-V compounds have proven to be strong contenders for extending high performance logic. However, most promising demonstrations of III-V FET/HEMTs have micron-scale source/drain spacing despite gate lengths on the nanometer scale. III-V semiconductor devices have historically relied on alloyed ohmic contacts which require large spacings to prevent shorting between the source and drain after alloying, where contacts can diffuse up to hundreds of nanometers.  This severely limits the scalability of III-V logic technology. Non-alloyed contacts offer a practical route to greatly reduce the III-V device footprint for application in future technology nodes.

In this talk, I demonstrate a route to non-alloyed contacts by shifting the pinned III-V Fermi level to reduce the metal/n-GaAs and metal/n-InGaAs Schottky barrier heights.  The Fermi level is controlled by the insertion of thin dielectrics in a metal-insulator-semiconductor (MIS) contact structure.  The MIS contact is studied across a wide range of metal and dielectric materials, and found to have great flexibility in the material selection. I will also discuss the use of bi-layer high-κ dielectrics, and report results which show that despite an overall thicker dielectric, there is an additional reduction in the barrier height and contact resistance beyond that of a single dielectric MIS.  This MIS contact is then integrated in an InGaAs MOSFET as a non-alloyed source/drain contact, though it can also be applied to Schottky Barrier FETs. I will conclude by discussing possible physical mechanisms of the observed barrier height reductions, by examining the effects of fixed charge and electronic dipoles. 

EE PhD Oral Examination - Rebecca Schaevitz, Thursday, June 2, 2011 at 3:00pm

Stanford University Oral Defense – Department of Electrical Engineering

 

Speaker: Rebecca K. Schaevitz

Advisor: Prof. David A. B. Miller

Date: Thursday, June 2, 2011

Time: 3:00 pm (refreshments at 2:45 pm)

Location: Allen-X Auditorium (formerly CIS-X Auditorium) - Room 101

 

Title

A Simple Quantum Well Electroabsorption Calculator for Germanium Quantum Well Devices

 

Abstract

Germanium is a unique material that is both CMOS-compatible and can be useful for optoelectronic devices. Leveraging existing CMOS technology, such as Reduced Pressure Chemical Vapor Deposition (RPCVD), Ge quantum wells are grown starting on pure Si substrates. The Ge wells exhibit strong electroabsorption behavior called the quantum-confined Stark effect (QCSE), which was unexpected in this material when it was first discovered at Stanford in 2005. With QCSE and Ge, we have the potential to develop highly CMOS-integrated optoelectronic modulators and bring optical interconnects to the short computer communication distances. However, given the novelty of the material system, we need the tools to design future devices that optimize performance.

 

In order to create a tool that could allow for future material and device design, we developed SQWEAC, or the Simple Quantum Well Electroabsorption Calculator. SQWEAC effectively models the Ge/SiGe quantum well electroabsorption spectra using simple physical models. The use of simple models drastically speeds up the computation time compared to more common methods like k.p and tight-binding. In this presentation, I will describe SQWEAC and show its effectiveness in modeling current Ge quantum well material. I will also present future modulator device concepts that could meet the strict criteria of power, size, extinction ratio and insertion loss, and allow us to bring optical interconnects to the chip level.