Carbon Nanotube Digital VLSI Circuits, Oct 2 (Fri), 12-1p, McCullough 115

Dear all

Please plan to attend the Nanosociety-Nanoelectronics seminar on Oct 2 (Fri) at 12p - 1p in McCullough 115.

Carbon Nanotube Digital VLSI Circuits

Speaker - Nishant Patil
Electrical Engineering
Stanford University

Abstract
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A CNT can be semiconducting or metallic depending upon the arrangement of carbon atoms. Typical CNT synthesis techniques yield ~33% metallic CNTs. Metallic CNTs create source-drain shorts in CNFETs resulting in excessive leakage (Ion/Ioff < 5) and highly degraded noise margins. We will present VLSI-compatible techniques for mitigating metallic CNT challenges. These techniques produce CNFET circuits with Ion/Ioff in the range of 103-105, and overcome the limitations of existing metallic-CNT removal techniques. We also demonstrate wafer-scale growth of (99.5%) aligned CNTs on single-crystal quartz and wafer-scale CNT transfer from quartz to silicon. Such an integrated approach enables experimental demonstration of cascaded CNFET logic circuits such as CNFET XNOR and CNFET D-latch.
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Pizzas would be served.