Gael Close's PhD oral examination --- Monday May 12 @ 10am

PhD oral examination

Title: On-Chip Demonstration of Carbon Nanotube Interconnects

Gael Close

Advisor: Prof. H.-S. Philip Wong

Date: Monday, May 12 at 10am, refreshments served at 9:45am

Location: Packard 101

ABSTRACT

Miniaturization in Electronics does not result in smaller high-performance chips.

Instead the chips remain the same in size, but they become exponentially

more complex-more devices and more complex wiring. An electronic chip

is only as good as its wiring. Today, copper interconnect wires are increasingly

becoming performance bottlenecks in integrated circuits. Copper was introduced

by chip makers in the late 90's to replace aluminum when the aluminum wires

started to limit chip performances, marking the beginning of the

"interconnect-centric era". What material is next beyond copper? Due to their

excellent electrical properties and small size, metallic carbon nanotubes (CNTs)

are promising materials for interconnect wires in future integrated circuits.

Indeed, simulations have firmly established CNTs as strong contenders

for replacing or complementing copper interconnects.

This talk builds on these modeling promises, and explores the use of CNT

interconnects from an experimental point of view. As a proof of concept,

this work culminates in the realization of the first digital integrated circuit

with CNT interconnects and silicon CMOS transistors. There remain

formidable challenges before a competitive CNT interconnect technology

can be implemented. However, the prototype chip described in the talk sets

a milestone by operating above 1 GHz, paving the way for future

multi-GHz nanoelectronics.

--
Gael Close
PhD Candidate
Center for Integrated Systems, CISX-300
Stanford University, California
+1-650-796-1241