Reminder: PhD Oral Examination: Shankar Swaminathan (Thursday, May 27th, 9:30AM)

                                                                                                                         Nanoscale atomic-layer-deposited high-k gate oxides on Germanium:

Interface engineering for highly-scaled MOS devices 

 Shankar Swaminathan 

Department of Materials Science and Engineering

Advisor: Dr. Paul C. McIntyre

Location: Bldg. 200 Rm. 002 (History Corner 200-002)

Date: Thursday, May 27, 2010

Time: 9:30 AM (refreshments served at 9:15 AM)

Germanium (Ge) has emerged as a promising candidate for surface channels in highly-scaled field-effect-transistors (FETs), as performance and reliability issues are likely to limit the use of conventional Si-based complementary-metal-oxide-semiconductor transistors. Lack of a high quality and stable thermal oxide of germanium has prompted interest in the use of high-k (high dielectric-constant) gate dielectrics on Ge channels. An interface layer (IL) between the high-k film and the Ge substrate appears to be necessary to avoid large defect densities characteristic of atomically-abrupt high-k (ZrO₂ or HfO₂)/Ge interfaces. Atomic layer deposition (ALD) is a useful high-k metal oxide film growth technique due to the precise nature of thickness control and uniformity of thickness for very thin films.  The use of ALD to synthesize deposited ILs interposed between the Ge channel and an overlying high-k layer has not been studied extensively. In this context, we present three highlights from our work: 

First, we show that a pre-ALD surface functionalization by oxidant dosing improves the electrical characteristics of Pt/4nm ALD-Al₂O₃/p-Ge devices, as opposed to a conventional precursor-first ALD process. In situ x-ray photoelectron spectroscopy in the ALD ambient reveals the influence of hydroxyl (-OH) termination of the Ge surface in passivating dangling bonds that lead to fast trapping. The evolution of Ge-O bonding states during this pre-pulsing process is correlated with the observed improvements in hysteresis, frequency dispersion of the gate capacitance, and the passivation of fast (band-edge) and slow (midgap) interface states.

Second, we present findings on the effects of scaling the physical thickness of the ALD-Al₂O₃ (down to 1 nm) on important electrical parameters such as interface state density (D_it), capacitance density, fixed charge and leakage current density. The ultrathin-ALD-Al₂O₃ / Ge interface shows no apparent interfacial suboxide (GeO_x) while retaining a low D_it of 2x10¹¹ cm^-2 eV^-1, indicating the potential of ALD-Al₂O₃ as an interface passivation layer.

Aggressive gate capacitance scaling necessitates the use of so-called "higher-k" dielectrics such as TiO₂ (k > 25). However, the conduction band offset (CBO) of the TiO₂/Ge interface is very low (~ 0.2eV), resulting in high gate leakage. We demonstrate that ultrathin (~ 1 nm) Al₂O₃ ILs, owing to their large bandgap (~ 6.6eV), enhance the CBO at the TiO₂/Ge interface, and reduce the gate leakage by 4 to 6 orders of magnitude at flatband. The Pt-gated bilayer devices exhibit excellent C-V characteristics down to a capacitance-derived EOT of 1.2 nm. The permittivity of the amorphous/nanocrystalline ALD-TiO₂ films was in the range of 32-35. Forming gas annealing is beneficial in lowering the interface state density via formation of monolayer-thickness interfacial GeO₂. Post-annealed devices exhibited a minimum D_it ~ 3x10¹¹ cm^-2 eV^-1 near midgap. Finally, we show that thermally activated electron transport into shallow defect states in the TiO₂ (~0.25eV below the CB edge) near the TiO₂/Al₂O₃ interface appears to be responsible for a temperature-dependent dispersion of the accumulation capacitance density. The passivation of these defects is important to fully realize the potential of novel bilayer high-kgate stacks on germanium channels.