Masaharu Kobayashi's Ph.D oral defense, seminar

Interface and Stress Engineering in Ge MOSFETs for High Performance CMOS

Masaharu Kobayashi
Advisor: Prof. Yoshio Nishi in Department of Electrical Engineering
Prof.. Krishna Saraswat in Department of Electrical Engineering

Date: Thrusday, April 23th, 2009
Time: 1:00pm
Location: CISX Auditorium

Abstract

         As silicon MOSFETs are aggressively scaled down to sub-100nm regime, the performance improvement becomes more challenging only by geometrical scaling because of parasitic resistance/capacitance and leakage/power consumption constraint. Mobility enhancement enables performance improvement additively to other scaling parameters so that high mobility channel material is regarded as a promising performance booster. Ge is one of the candidates because of its high electron/hole mobility, process compatibility with Si LSI technology and low temperature process due to low melting point. However, there are several device/process issues to be solved for high performance CMOS with Ge. In this seminar, I will report three achievements contributing to Ge MOS technologies: (1) low interface states GeO2 formed on Ge by radical oxidation for reliable gate stack, (2) Fermi level depinning and contact resistance reduction at metal/Ge contact and (3) uniaxial stress engineering for electron mobility enhancement in Ge NFETs.
(1) A number of surface passivation methods have been used for Ge gate stack, however, none of them provides as low interface state density as Si. GeO2 has now been reconsidered as an interfacial layer for high-k/Ge gate stack. In this work, novel radical oxidation method was introduced for interfacial GeO2 growth, which enabled low interface state density in high-k/GeO2/Ge gate stack, 1x1011cm-2V-1.
(2) Low contact resistance in metal/n-Ge contact is challenging because Fermi level of metal is strongly pinned near the valence band edge of Ge. Preventing wave function penetration into Ge and reducing the effect of metal induced gap state of Ge are the key to the Fermi level depinning. In this work, we demonstrated Schottky barrier height modulation and contact resistance reduction by inserting thin interfacial layer between the metal and the Ge.
(3) According to the bulk mobility, electron mobility enhancement in Ge is only 2x higher over Si, and has to be boosted by stress. In this work, we systematically applied stress to different channel directions and achieved electron mobility enhancment in Ge NFETs. Theoretical simulation and experiments clarified the physical mechanism of electron mobility enhancement by uniaxial stress.


Masaharu Kobayashi
Ph.D candidate
Department of Electrical Engineering
Stanford Unversity
TEL:650-521-4260
E-mail:masaharu@stanford.edu