Reminder :: PhD Oral Examination :: Matthew Messana (Today, June 24, 2010, 1:30pm)

Stanford University Ph.D. Oral Examination

Department of Mechanical Engineering

 

Title: Development and Characterization of a Wafer-Scale Packaging Technique for Stable Large Lateral Deflection MEMS

Speaker: Matthew Messana

Advisor: Professor Thomas Kenny

Date: Thursday, June 24th, 2010

Time: 1:30pm (Refreshments and snacks at 1:15pm)

Location: Allen Building (formerly CIS-X) Auditorium, Room 101

 

 

Abstract:

 

Microelectromechanical systems (MEMS) are becoming very popular in our everyday lives. They are showing up more and more in automobiles, cell phones, televisions and many other places. The packaging of these devices is critical to their performance and reliability and must be carefully considered in their overall system design. Due to strict requirements and the fragile nature of these devices, the packaging often represents a significant portion of the total cost of a MEMS product.

 

Stanford University, jointly with Bosch, developed a wafer-scale encapsulation method in which MEMS devices are encapsulated as a part of their fabrication. This process, now used by SiTime, has been dubbed the ‘epi-seal’ process by virtue of its use of an epitaxial silicon reactor to seal the cavities containing the devices. Devices are cleaned in-situ in the epitaxial silicon reactor just prior to sealing, resulting in a package environment that is very clean and stable. Because this is a batch process, the overall packaged device cost is very low. One significant limitation with this process, however, is that devices are limited to small (less than 2µm) trenches, thus prohibiting large displacements and common MEMS structures such as comb drives.

 

In this presentation, I will discuss a method for expanding the design rules of the epi-seal process to include large lateral deflection structures, while still maintaining the desirable qualities of the original process. The method involves fusion bonding a sacrificial wafer to a silicon-on-insulator (SOI) wafer with devices already etched in it. The sacrificial wafer is thinned via grinding and polishing, similar to the fabrication of an SOI. Cavities are vented through the thinned wafer and devices released using HF vapor. Like the epi-seal process, the devices are then cleaned and sealed in the epitaxial silicon reactor. The resulting MEMS are fully encapsulated in single crystal silicon that is suitable for CMOS integration directly above the devices. Many widely varying devices were produced using this process in the Stanford Nanofabrication Facility (SNF) with high yield. I will discuss some of these devices and how we used them to characterize the package.