Thin, terraced SiO2/Si substrates for MOS capacitors

Hello,

Does anyone have a process for making MOS capacitor quality, 10-1 nm thick stepped SiO2 on Si? The lateral step dimension just needs to be such that all 10 steps can be accommodated on a 4" wafer.

Also, any information on how to make wedding cake (5-1 nm) SiO2 would be helpful as well.

Thanks in advance,

Melody Grubbs
PhD Candidate
Materials Science and Engineering
Stanford University