Friday, September 17, 2010

Reminder: TODAY : EE PhD Oral Examination - Shyam Raghunathan - 10.15 am, CIS-X Auditorium

EE Ph.D. Oral Examination

Scaled Planar Floating-Gate NAND Flash Memory Technology:
Problems and Novel Solutions

Shyam Raghunathan

Advisor: Prof. Krishna Saraswat
Co-Advisors: Prof. Yoshio Nishi, Prof. Tejas Krishnamohan
Chair: Prof. Butrus Khuri-Yakub
Date: Sept 17th, Friday, 10.30 am (Refreshments at 10.15 am)
Venue: Allen CIS-X Auditorium

Flash memory is the most widely used non-volatile information-storage
technology today. NAND Flash memories are ubiquitous in their use as
portable storage media in cellphones, cameras, music players, and
other portable electronic devices. In addition, NAND Flash memory has
recently seen rapid adoption as Solid-state drives (SSD) in place of
Hard-disk drives (HDD) in modern personal computers and data servers.
In addition to greater speed, SSDs also provide much lower power
consumption compared to HDDs.

       The NAND Flash memory device, consisting of a floating-gate
transistor cell, is the most aggressively scaled electronic device, as
evidenced by ever-increasing memory capacities. In this talk, we will
examine some problems in the continued scaling of these structures and
discuss novel solutions to overcome them.

       (1) Firstly, we investigate scaling of the conventional
poly-silicon floating-gate, aimed at reducing cell-to-cell
interference.  We demonstrate experimentally a new reliability concern
for the first time, arising due to programming current becoming
increasingly ballistic through ultra-thin poly-silicon floating-gates.
We also experimentally demonstrate doping-related issues in the
poly-silicon floating-gate.

       (2) We then demonstrate a novel metal-based floating-gate cell
for the first time, designed to overcome the problems discussed above.
We explore factors that influence the choice of metal and we
demonstrate excellent functionality in ultra-thin metal floating-gate
cells scaled down to 3 nm TiN floating-gate thickness, thus greatly
reducing cell-to-cell interference.

       (3) Finally, in order to facilitate continued scaling of the control
dielectric, we explore replacement of the conventional Oxide-Nitride
dielectric with high-k dielectric materials. We demonstrate
integration of both poly-silicon and metal floating-gate cells with
Al2O3 high-k control dielectric, thereby enabling the planar
floating-gate cell.

No comments: