Re: Problem p5000etch SNF 2008-09-25 15:57:06: endpoint PC not working

Power off and on endpoint pc computer and it went
through cal w/out problem.

Ti etch at wbmetal

Hi,

Does anyone know the etch rate of Ti in the 5:1:1 H2O:H2O2:NH4OH bath at
wbmetal? Also, what's the selectivity to photoresist (3612) and Si? If
there's an easier wet etch to use, that info would be helpful, too.

Thank you,
John

Veeco AFM seminar

All,

Mayur Savla the Veeco Bay Area AFM Applications Engineer, will hold a
seminar on:

Wednesday, October 8 at 2:30 to 3:15 PM
Allen Center for Integrated Systems
CIS-X Cypress Auditorium (CISX101).

He will discuss the best practices and set-up tips for optimizing
scan parameters for surface roughness and step height measurements,
Force curve measurements, Phase imaging, Fluid imaging and Electrical
Measurements using AFM.

Registration is required if you want to win the free sample pack of
AFM tips. See the flyer for instructions.

If you have any questions, please feel free to contact me or Paul
Charell at <mailto:pcharell@veeco.com>pcharell@veeco.com.

Regards,
Ed

damage of Al2O3 by photoresist stripper?

Hi all,

 

Does anyone know if the photoresist stripper Microposit 1165 attacks Al2O3?

 

Thanks,

Byungha

Problem p5000etch SNF 2008-09-25 15:57:06: endpoint PC not working

CH. B nit-spacer with "nit_spacer.alg". even after reboot, the endpoint program will not start graphing when RF turns on.

Re: Shutdown p5000etch SNF 2008-09-25 12:13:35: wafer stuck in chamber B

Removed broken wafer from the chamber. It looks like a stress break ?? Wafer placement checked OK. Ran 6 wafers, 2 faulted for high He leak rate.

Reminder: Cleanliness & Contamination Meeting, Thursday, 9/25, 3 pm

Hi all --

Just a reminder. For details:

http://snf.stanford.edu/cgi-bin/ezmlm-cgi?mss:3413:200809:phkllicgjinehokifeok

Your SNF Staff

--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu

Shutdown p5000etch SNF 2008-09-25 12:13:35: wafer stuck in chamber B

process did not start due to He leak back rate too high.
ended recipe but wafer did not come out of chamber.
loadlock door is left open by the tool.

Comment p5000etch SNF 2008-09-24 19:03:20: Update Ch.A particles

Completed major chamber wet clean (removed and cleaned the process kit) + wiped down the entire chamber.
- Particle test still bad using Ch.A Metal recipe
- Ran a variety of different test to partition the source of the particles. The source of particle is NOT the gases, NOT the loadlock, NOT the wafer transfer.
- Particles are deposition only when the plasma is on.
- We will continue to troubleshoot tomorrow. Next to try is to run a plasma process using only an inert gas. Also need to investigate if the showerhead's anodization has worn

Hydrogen Etching

Hi all,

Does anyone have the experience of Hydrogen Etching to produce atomically flat surfaces? Actually, I have SiC with scratches which needs Hydrogen Etching based on the papers.

If you give advice about the procesure and the location of the equipment, I will appreciate it.

Thanks in advance.

Best,

Sangwon

DI Water back on!!!

Thanks for your patience -- DI water is now available to the lab.

Your SNF staff

--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu

Problem p5000etch SNF 2008-09-24 14:28:52: CH A down for major clean

Ran 1000A ox wafer, CH A TImed Metal- particles
Ran 1000 ox wafer, CH B Oxide- no particles
Elmer will do major wet clean- chamber, componets....

Problem p5000etch SNF 2008-09-24 10:29:43: ch. A still leaves particles on wafer

much cleaner than before chamber A was cleaned but has particle problem. "CH. A. timed" 30sec.

Today: OSA/SPIE Seminar: Steven Horne / SolFocus, Inc. - Wed. 9/24, 4pm, Ginzton AP 200

A quick reminder: 

The Optical Society of America/SPIE Stanford Student Chapter, and the Stanford Photonics Research Center present:

"Building the next-generation concentrating photovoltaics technologies for large-scale electricity generation"
Speaker: Steven Horne, SolFocus Inc.

Today

4:15pm, Ginzton/Applied Physics Building, AP 200
Refreshments at 4:00pm

Abstract: Concentration Photovoltaics (CPV) is a new and interesting approach to solar electricity generation, and promises very low cost. Long a lab and startup company phenomenon, CPV is finally emerging as a viable industry, with the first significant field installations being installed this year. SolFocus has just completed its first half megawatt field in Spain, and is committing to build a high volume manufacturing facility over the next twelve months. This talk presents an overview of the field, and covers the thought process that led to the SF-1000, SolFocus' first product.

DI Water shutdown - ON again, for today

Dear labmembers --

We're back on for this morning's DI water shutdown after all.
(Realizing this doesn't inspire a lot of confidence in Stanford's
planning ability, we ask that you please bear with us -- the problem
seems to have been miscommunication at levels outside of SNF.) The
target for turn-on is still noon, but as the vendor is getting a late
start, there may be a delay. Please watch for a labmembers announcement.

Your SNF Staff

--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu

DI water upgrade - not today -- now Friday

Dear Labmembers --

Many apologies... The DI water system upgrade is now scheduled for
this Friday. Again, this will be from 7 am to noon. Systems in the lab
are OK to use this morning.

Your SNF staff

--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu

IrO2 Etching

 Hi all,

 I am trying to make an electrode using Iridium oxide (IrO2).
 Could anyone please tell me the dry etching method of IrO2 ?

 I would appreciate it if you give me some tips on the dry etching.
 Thanks.

 Best,

 Wanki

Re: Comment p5000etch SNF 2008-09-17 10:08:35: Ch.C update

truned into problem report....

Problem p5000etch SNF 2008-09-23 14:29:51: CH C down

We should have the clamp ring by 10/3/08.

Re: Problem p5000etch SNF 2008-07-07 17:19:15: Ch. C helium leak rate too high

clamp will be replaced in early Oct.

Re: Problem p5000etch SNF 2008-07-08 15:26:21: Ch.C is down

newer update in comments

Re: Comment p5000etch SNF 2008-08-19 10:54:43: Ch.B is UP

yep- still is...

Comment p5000etch SNF 2008-09-23 14:24:20: CH B qual after shower head clean

Ox etch rate = 3532A/min
PR etch rate = 2230A/min
Ox:PR selectivity = 1.6:1
Uniformity +/- 6.4%
Top to bottom uniformity = ~10%
Much better than when clamp materials first swapped.

Re: Comment p5000etch SNF 2008-09-22 20:53:37: Good Uniformity

that's about what I got, too.

Re: Problem p5000etch SNF 2008-09-19 15:27:40: etch non-uniformity still bad after 30min. etch (5 wafers)

non-uniformity is getting better. Quals results posted in comments.

Re: Comment p5000etch SNF 2008-09-17 10:21:11: Ch.A is up

archived

Comment p5000etch SNF 2008-09-23 14:18:48: test run after CH A clean-up

Look fine. No particles in resist regions- some in field, but test wafer had a terrible litho pattern so might be pr spots. Did not look like particle.

Re: Problem p5000etch SNF 2008-09-19 18:03:11: ch A leaving residual

ran test after clean. Posted.

Re: Problem p5000etch SNF 2008-09-19 12:45:11: CH B qual- uniformity not good

new qual posted...

Re: Comment p5000etch SNF 2008-09-23 09:11:50: Update Ch.A particles

archived- test results posted in comments....

Cleanliness and Contamination Policy Meeting, Thursday, 9/25, 3 pm

Greetings Labmembers --

As many of you may be aware (some, very keenly aware!), the SNF AdCom
met two weeks ago to discuss our cleanliness and contamination policy at
SNF. The AdCom, or Advisory Committee, consists faculty and industrial
PI's whose research groups generate the most activity in the lab. In
short, the request was for a system that would allow for more
flexibility in processing, but without risking basic device
functionality, process stability, and most importantly, safety.

Please be assured that NO decisions on policy change have been made.
The objective is to establish the rationale for the cleanliness policy,
concerns for contamination, and process requirements which may routinely
fall outside the routine definitions. Everyone is aware that even small
changes to our system can have lasting ramifications. However, it is
clear that the current system does not meet the needs of most of our
labmembers.

Following on the AdCom's directive, there will be a Labmembers' meeting
where a summary of the discussion will be presented and inputs from the
lab community invited; from this, we plan to set the stage for a working
group on contamination policy. This Labmembers' meeting will take place
this Thursday, Sept. 25, at 3 pm in the CISX Auditorium.

Your SNF Staff

--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu

Re: Problem p5000etch SNF 2008-09-22 17:23:45: chamber B offline

Another user placed Chamber B online and recovered the wafer

Comment p5000etch SNF 2008-09-23 09:11:50: Update Ch.A particles

Wet cleaned the chamber. Cleaned the showerhead. Ran 4 wafer using the Ch.A metal recipe with no problems.

warning from p5000etch-pcs@snf.stanford.edu

Hi! This is the ezmlm program. I'm managing the
p5000etch-pcs@snf.stanford.edu mailing list.

I'm working for my owner, who can be reached
at p5000etch-pcs-owner@snf.stanford.edu.

Messages to you from the p5000etch-pcs mailing list seem to
have been bouncing. I've attached a copy of the first bounce
message I received.

If this message bounces too, I will send you a probe. If the probe bounces,
I will remove your address from the p5000etch-pcs mailing list,
without further notice.

I've kept a list of which messages from the p5000etch-pcs mailing list have
bounced from your address.

Copies of these messages may be in the archive.

To retrieve a set of messages 123-145 (a maximum of 100 per request),
send an empty message to:
<p5000etch-pcs-get.123_145@snf.stanford.edu>

To receive a subject and author list for the last 100 or so messages,
send an empty message to:
<p5000etch-pcs-index@snf.stanford.edu>

Here are the message numbers:

2215
2227

--- Enclosed is a copy of the bounce message I received.

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Subject: Undelivered Mail Returned to Sender
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Comment p5000etch SNF 2008-09-22 20:53:37: Good Uniformity

non uniformity is within 10%

Problem p5000etch SNF 2008-09-22 17:23:45: chamber B offline

i can't unload my wafers, it is stuck in the wafer loading station

DI Water Shutdown, Wed. AM

Dear Labmembers --

The DI water pump which supplies our lab will be replaced on Wednesday
morning, starting at 7 am and should be done by noon, if not before
then. During this time, DI water will unavailable. This affects the
following stations:

Wet stations: wbdiff, wbsilicide, wbnonmetal, wbnitride, wbgeneral,
wbgen2, wbmiscres, wbgaas, wbmetal

Other stations: svgdev, svgdev2, kscoat, wafersaw, cmp

These tools have been reserved for this time and will be unavailable.
Please plan your processing around this shutdown. We apologize for the
inconvenience - but this should give us a more reliable and serviceable
DI supply.

Thanks for your attention --

You SNF Staff

missing wafers

Dear labmembers,

Sorry for bothering. I am looking for a wafer box which contains 15 SOI wafers. I brought it to the clean room last Thursday evening. I checked around the lab today and couldn't locate it. It is vacuum packaged in a clear plastic bag. If you happen to see such a wafer box please let me know.

Thanks!

Steve

SAM (Scanning Acoustic Microscope)

Hi labmembers,

I'm looking for someone (institution or company) that has SAM (Scanning Acoustic Microscope), in order to image voids and defects in bonded wafer pairs. Please let me know if you have experience, or contacts relating to SAMs.

Ironically, the technique was developed at Stanford, yet there are none on campus (as far as I know).

Cheers,

Filip

--------------------------------------
Ph.D. Candidate, Stanford University
Department of Electrical Engineering
Center for Integrated Systems
B-103, 420 Via Palou
Stanford, CA 94305

stable recipe for Schottky contacts on n-type Si?

Hello all:
Does anyone have a good, repeatable recipe for making Schottky
contacts to n-type Si? I have been using shadow-masking to pattern Cr
and Al contacts on n-type SOI, and the dark I-V characteristics of my
diodes change with time (as does the photoresponse). A lot of the
literature suggests using Al, but with a work function about equal to
the conduction band level of Si, that seems like a bad choice, and the
diodes I have made with Al look unsurprisingly ohmic and highly
variable from diode to diode (anywhere from nA to µA of dark current
at 1V). Am I just that bad at microfabbing? :-)

Any suggestions people have for any deposition and annealing steps
would be greatly appreciated. Thanks in advance for your help!

Sincerely,
Alex

Comment p5000etch SNF 2008-09-22 11:35:10: Update Ch.B uniformity

Cleaned the showerhead and replaced showerhead o-ring.

Process Clinic: Today (Mon) 2-4 pm, cubicle area

Hi all --

Just a reminder there's a Process Clinic today, Monday, from 2-4 pm. We
meet in the cubicle area outside of Maureen's office. Bring your
process flows, device layouts and Special Materials requests -- staff
and lab members will be on hand to help brainstorm.

Your SNF Staff

--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu

Problem p5000etch SNF 2008-09-19 18:03:11: ch A leaving residual

lots of residue particles in field after 10-20sec etch of Al.
used "ch. A. timed"

Problem p5000etch SNF 2008-09-19 15:27:40: etch non-uniformity still bad after 30min. etch (5 wafers)

280A difference in etch rate during a 1600A etch --> 17.5%

OSA/SPIE Seminar: Steven Horne / SolFocus, Inc. - Wed. 9/24, 4pm, Ginzton AP 200

The Optical Society of America/SPIE Stanford Student Chapter, and the
Stanford Photonics Research Center present:

"Building the next-generation concentrating photovoltaics technologies
for large-scale electricity generation"
Speaker: Steven Horne, SolFocus Inc.

Wednesday, September 24, 2008
4:15pm, Ginzton building, AP 200
Refreshments at 4:00pm

Abstract: Concentration Photovoltaics (CPV) is a new and interesting
approach to solar electricity generation, and promises very low cost.
Long a lab and startup company phenomenon, CPV is finally emerging as
a viable industry, with the first significant field installations
being installed this year. SolFocus has just completed its first half
megawatt field in Spain, and is committing to build a high volume
manufacturing facility over the next twelve months. This talk presents
an overview of the field, and covers the thought process that led to
the SF-1000, SolFocus' first product.

About our Speaker: Steve Horne is cofounder and CTO of SolFocus inc, a
product manufacturer in the Concentration Photovoltaic (CPV) field.
Steve started his engineering career commissioning large coal burning
powerplant in Australia before migrating to Silicon Valley and the
world of microelectronics and precision mechanics. He is now atoning
for his early sins in the renewable energy world.

Problem p5000etch SNF 2008-09-19 12:45:11: CH B qual- uniformity not good

Etch rate of oxide is 3507A/min
Etch rate of resist is 2262A/min
Selectivity of SiO2 to PR is 1.6:1
But, top to bottom uniformity is bad, about 20%.

Re: Shutdown p5000etch SNF 2008-09-19 11:11:17: Needs a qual

Qual completed.
Etch rate of ox = 3507A/min
Etch rate of resist = 2262A/min
Selectivity = SiO2:PR = 1.6:1
However, the ox uniformity top tp bottom is quite bad- 20%.
The uniformity is much worse, so I can't reccommend swapping the quartz for vespel.

Shutdown p5000etch SNF 2008-09-19 11:11:17: Needs a qual

Chamber B needs to be qualed

Re: Problem p5000etch SNF 2008-09-18 16:41:48: software unresponsive

Error was already cleared. This resulted from the handling errors from chamber B.

Re: Problem p5000etch SNF 2008-09-18 19:21:44: recoverd piece of wafer

Found the wafer clamp broke the wafer. Removed wafer pieces and wiped down the electrode.
Changed the configuration of the 2 piece clamp assembly so that the part made out of vespel is clamping the wafer instead of the quartz. I believe this is the cause of our intermittent wafer breakage and "mouse bites" problem .

Reminder: Labmembers' Meeting Today, 9/19, 11 am, CISX Aud.

Hi all --

Just a reminder of the Labmembers' meeting today, 11am, in the CISX
auditorium. On the agenda --

- General announcements
- Quality Circle updates
- Annual rate increase for 2008-09
- EE410 Redesign project
- Contamination policy update program
- Tylanbpsg summary
- Other project updates

All this, and more.

Everyone in the lab community is welcome.

Your SNF Staff

Problem p5000etch SNF 2008-09-18 19:21:44: recoverd piece of wafer

1/3 of the wafer is missing; likely to be in CH. B
could someone please remove it?
Thanks.

Problem p5000etch SNF 2008-09-18 16:41:48: software unresponsive

Upon trying to remove my wafer, I received the error "The load chamber task did not acknowledge the sequencer". The message "Select Error Processing Option" flashes on the screen on the System page, but I am unable to abort or put the system in manual mode, or open the door. My wafer is currently in the cassette in the loading station.

missing lab notebook

Dear labmembers,
My lab notebook has gone missing...I don't recall put it back to my
bin yesterday.
It's a 51/2"X81/2" notebook and has my name on the upper right corner.
If you see it in the lab or accidently took it please let me know.

Thank you very much,
Li-Wen

About to release an updated version of Coral .....

SNF Lab Members:

In the next day or so, we plan to release a new version of Coral.  One thing that will jump out at you is the fact that the old, familiar stoplight equipment icons have been replaced.  In particular, both because some folks find it difficult to easily distinguish color .... particularly in either yellow lighting or in the low-light conditions often found in the Raith and ebeam room .... we've changed the icons so that each have different colors and shapes.

There is also a menu item (under the "Help" menu item at the right side of the menu items) named "Icon Help" that will pop up the following window to explain the meaning of each of the icons.



This updated version will likely appear either early tomorrow morning or fairly early during the weekend.

As usual, please let us know if you encounter any problems or have any concerns.

Thank you for your ongoing support,

John

JA Woollam Short Course Announcement

Lab Members,

If you want to strengthen your Spectral Ellipsometer skills, here is
an excellent opportunity. Everyone I have talked with who have
attended aJA Woollam training classes have given great reports on the
lectures, contents and the hands on training.

Regards,
Ed

>X-Sieve: CMU Sieve 2.3
>Delivered-To: edmyers@stanford.edu
>Date: Wed, 17 Sep 2008 14:55:49 -0500
>To: Veronica Inlow <vinlow@jawoollam.com>
>From: Veronica Inlow <vinlow@jawoollam.com>
>Subject: New Short Course Announcement
>
>
>Dear J.A. Woollam Co. Customers,
>
>This fall we are offering two new short courses. Both courses will
>be taught at the Intermediate to Advanced Level and are intended for
>customers with over two years of experience with WVASE32 software or
>have already taken our Standard Short Course.
>
>The first course will be held November 17-18, 2008 at our facility
>in Lincoln, Nebraska. It offers a refresher on the different
>modeling approaches available in WVASE32. We will also teach when to
>use the different models. The second course will he held November
>20-21. It will cover how to measure anisotropic materials. Please
>see the attached registration form for more details. Note, these
>courses are not intended for users that work with other software
>packages, such as CompleteEASE.
>
>If you would like to attend one or both courses, just fill out the
>registration form and fax to me. The deadline to register is October
>31, 2008. If you have any questions, please do not hesitate to contact me.
>
>Sincerely,
>
>Veronica Inlow
>
>*******************************
>Veronica Inlow
>Marketing Coordinator
>J. A. Woollam Co., Inc.
>645 M Street, Suite 102
>Lincoln, NE 68508
>vinlow@jawoollam.com
>Phone: (402)477-7501 x101
>Fax: (402)477-8214

SiON deposition at SNF

Dear lab members,

 

 Is there a tool for SiON deposition at SNF? I am hoping to deposit 10-100nm thick SiON on top of LPCVD SiO2.

 

Thanks,

SangBum

Comment p5000etch SNF 2008-09-17 10:21:11: Ch.A is up

Re: Problem p5000etch SNF 2008-09-15 17:52:23: sometimes leak rate drops back to 1

Root cause of burned resist:
- Wafers were intermittently sliding off the electrode during the load cycle resulting in a He leak rate of around 6 sccm.
- Found the backside He flow was turning on before the clamp ring was in the process position.
- Adjusted the clamping speed so that the wafer is fully clamped before the He turns on.
- Ran 25 wafers with no problems. Leak rate was consistently around 1.5 sccm.
- Lowered the backside He fault tolerance from 10 sccm to 3 sccm.

Comment p5000etch SNF 2008-09-17 10:08:35: Ch.C update

We should have the clamp ring by 10/3/08.

Re: Comment p5000etch SNF 2008-07-22 14:20:05: Chamber C ring

Archived

Re: Comment p5000etch SNF 2008-07-30 10:06:44: Update

Heat exchanger has not shut-off in more than 1 month.

Re: Comment p5000etch SNF 2008-09-10 15:37:26: wafer sometimes not sitting right after the process

Adjusted the cassette elevator height

Re: Comment p5000etch SNF 2008-09-15 15:14:16: Ch.A update

Archived

Re: Comment p5000etch SNF 2008-09-13 14:39:33: CH. A seems to be fine

Root cause of burned resist:
- Wafers were intermittently sliding off the electrode during the load cycle resulting in a He leak rate of around 6 sccm.
- Found the backside He flow was turning on before the clamp ring was in the process position.
- Adjusted the clamping speed so that the wafer is fully clamped before the He turns on.
- Ran 25 wafers with no problems. Leak rate was consistently around 1.5 sccm.
- Lowered the backside He fault tolerance from 10 sccm to 3 sccm.

Re: Comment p5000etch SNF 2008-09-12 15:10:04: Ch.A needs to be tested

Archived

Re: Comment p5000etch SNF 2008-09-11 14:48:28: CH. A is down

Archived

Re: Problem p5000etch SNF 2008-09-10 20:21:56: CH A burns silicon wafer!!

Root cause of burned resist:
- Wafers were intermittently sliding off the electrode during the load cycle resulting in a He leak rate of around 6 sccm.
- Found the backside He flow was turning on before the clamp ring was in the process position.
- Adjusted the clamping speed so that the wafer is fully clamped before the He turns on.
- Ran 25 wafers with no problems. Leak rate was consistently around 1.5 sccm.
- Lowered the backside He fault tolerance from 10 sccm to 3 sccm.

Re: Comment p5000etch SNF 2008-09-10 18:51:58: CH. A. Helium leak down to 0.7 and no resist burns!

Archived

Re: Comment p5000etch SNF 2008-09-09 10:37:43: Ch.A burnt resist update

Archived

Re: Problem p5000etch SNF 2008-09-05 15:34:33: Burned resist

Root cause of burned resist:
- Wafers were intermittently sliding off the electrode during the load cycle resulting in a He leak rate of around 6 sccm.
- Found the backside He flow was turning on before the clamp ring was in the process position.
- Adjusted the clamping speed so that the wafer is fully clamped before the He turns on.
- Ran 25 wafers with no problems. Leak rate was consistently around 1.5 sccm.
- Lowered the backside He fault tolerance from 10 sccm to 3 sccm.

Re: Problem p5000etch SNF 2008-09-05 15:24:31: CH. A. resist burn, high He leak rate

Root cause of burned resist:
- Wafers were intermittently sliding off the electrode during the load cycle resulting in a He leak rate of around 6 sccm.
- Found the backside He flow was turning on before the clamp ring was in the process position.
- Adjusted the clamping speed so that the wafer is fully clamped before the He turns on.
- Ran 25 wafers with no problems. Leak rate was consistently around 1.5 sccm.
- Lowered the backside He fault tolerance from 10 sccm to 3 sccm.

Re: Problem p5000etch SNF 2008-08-31 11:12:25: burned photoresist

Root cause of burned resist:
- Wafers were intermittently sliding off the electrode during the load cycle resulting in a He leak rate of around 6 sccm.
- Found the backside He flow was turning on before the clamp ring was in the process position.
- Adjusted the clamping speed so that the wafer is fully clamped before the He turns on.
- Ran 25 wafers with no problems. Leak rate was consistently around 1.5 sccm.
- Lowered the backside He fault tolerance from 10 sccm to 3 sccm.

Labmembers' Meeting Friday, 9/19, CISX Auditorium

Greetings labmembers --

Just a reminder that there's a Labmembers' Meeting this Friday, Sept.
19, at 11 am in the CISX Auditorium. On the agenda:

- General announcements
- Quality Circle updates
- Annual rate increase for 2008-09
- EE410 Redesign project
- Contamination policy update program
- Tylanbpsg summary
- Other project updates

That and more. Everyone in the lab community is welcome.

Your SNF Staff

--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu

Re: Shutdown p5000etch SNF 2008-09-16 09:39:21: Troubleshooting Ch.A

Completed troubleshooting. Ch.A is still down for intermittent high backside He leak rate.

thin SOI doped wafers

Hello!

I am wondering if you know where I can buy thin SOI wafers.
Here is my spec:
Diameter: 100mm
Si device layer: 150-200nm, doped
BOX: around 400nm

I contacted SOITEC and University wafers, but it seems they do not have such a stock.
It would be great if you know some other vendors.

Thank you very much and sorry for filling up your inbox.

best,
Kyeongran

Shutdown p5000etch SNF 2008-09-16 09:39:21: Troubleshooting Ch.A

Problem p5000etch SNF 2008-09-15 17:52:23: sometimes leak rate drops back to 1

most of the runs, the leak rate is about 6, which burns resist, but one in the ten runs I did had a leak rate of 1. Again, the etch rate of the high leak rate is 30% slower than that of the low leak rate.

Comment p5000etch SNF 2008-09-15 15:14:16: Ch.A update

First wafer ran (Ch.A metal recipe)after the reset was OK with a He leak rate of ~ 1.5 sccm. Subsequent wafers had a leak rate of ~ 6 mT and burnt the resist (no burn marks on the backside of the wafer). It looks like one of the lip seals is bad again. Kevin decided to run anyway. Need to find out what is causing the seals to fail prematurely.

Re: Problem p5000etch SNF 2008-09-14 15:52:39: errors

Analog signals were not updating on the screen. Reset the system and restarted all the chambers. Ran 4 wafers through both Ch.A and Ch.B. System faulted for I/O blocked during the unload. Adjusted the cassette elevator height. System ran OK after the adjustment.

Re: Problem p5000etch SNF 2008-09-13 16:25:47: turbo is off

Analog signals were not updating on the screen. Reset the system and restarted all the chambers. Ran 4 wafers through both Ch.A and Ch.B. System faulted for I/O blocked during the unload. Adjusted the cassette elevator height. System ran OK after the adjustment.

Re: Problem p5000etch SNF 2008-09-13 14:41:46: error message: capacitive sensor 1 and 2 not working

Analog signals were not updating on the screen. Reset the system and restarted all the chambers. Ran 4 wafers through both Ch.A and Ch.B. System faulted for I/O blocked during the unload. Adjusted the cassette elevator height. System ran OK after the adjustment.

Problem p5000etch SNF 2008-09-14 15:52:39: errors

multiple errors: capacitive sensor, helium
dummy wafer in chamber.

Problem p5000etch SNF 2008-09-13 16:25:47: turbo is off

the wafers do not transfer from the loader into the chamber. checked the chamber and turbo was off.

Problem p5000etch SNF 2008-09-13 14:41:46: error message: capacitive sensor 1 and 2 not working

Comment p5000etch SNF 2008-09-13 14:39:33: CH. A seems to be fine

I ran two wafers and the leak rate was low, etch rate was normal, thanks!

Comment p5000etch SNF 2008-09-12 15:10:04: Ch.A needs to be tested

Replaced burnt pin lip seal.

CIS BBQ

Greetings everyone!

We trust that those of you who were able to make it enjoyed yesterday's
BBQ on the patio.

I'd like us to take a moment to thank the CIS program (Dr. Dasher and
Prof. Nishi) for generously hosting this event. And Maureen Baran,
Marjorie Alfs, and Miho Nishi for making it all happen.

It was a beautiful day -- and a nice break before students return!

Mary

--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu

Re: Comment p5000etch SNF 2008-08-20 09:34:12: Ch.A is UP

Archived

Comment p5000etch SNF 2008-09-11 14:48:28: CH. A is down

Vacuum pump purge is not turning on

Power back on .....

SNF Lab Members:

Power has been restored following the replacement of one of the main
800A circuit breakers. As of 11:45 many of the affected tools are back
on and their shutdowns have been cleared.

There are a handful of tools that have cryopumps that will need a full
regeneration that will take several hours .... that will include the
ebeam, metalica, and innotec. A few of the other tools that need
vacuum, including sts, ald, stsetch2, and matrix should be up shortly
after lunch.

Please contact me if you see tools other than these that have not yet
been returned to service.

Thank you for your continued support,

John

Problem p5000etch SNF 2008-09-10 20:21:56: CH A burns silicon wafer!!

Helium leak rate was 0.6 for 2 wafers and it jumped back to
5.9 for the next 4 wafers and on the 3rd one, the back side of silicon wafer was burned black!
And for all of the wafer, it's consistent that the left side of the wafer has higher etch rate and the right edge of the wafer had ZERO etch rate.
Also, the etch rate when there was 0.6 helium leak was 30% faster than that of 5.9 helium leak.

Comment p5000etch SNF 2008-09-10 18:51:58: CH. A. Helium leak down to 0.7 and no resist burns!

Thanks for changing the lip seal

Comment p5000etch SNF 2008-09-10 15:37:26: wafer sometimes not sitting right after the process

wafer maybe a bit out of the cassett after the process. it causes IO problem when you are trying to unclamp the cassett. just open the door and pull your wafer into the cassett.

VM-651 to spare?

Hi All,

 

Does anyone have some VM-651 adhesion promoter for Polyimide PI-2611 that I could use? I need less than 1 mL.

 

Thanks for your help,

 

nh

--
Nahid Harjee
Ph.D. Candidate
Electrical Engineering
Stanford University
408-761-8651

Re: Problem p5000etch SNF 2008-09-09 18:56:17: "Can't start with wafer on blade" error

Opened the chamber and recovered the user's wafer. Wet cleaned the electrode and ran 5 wafers using Jim Ox recicpe.

Re: Problem p5000etch SNF 2008-09-09 16:00:25: Wafer stuck in Ch. B

Opened the chamber and recovered the user's wafer. Wet cleaned the electrode and ran 5 wafers using Jim Ox recicpe.

Update on yesterday's lab evacuation

Dear Labmembers:

As many of you may be aware, there was an an evacuation of the lab
yesterday around 4:30 pm for a chlorine-like smell. Thankfully,
everyone got out in an orderly fashion and there were no injuries.
After about 30 minutes, the lab air had cleared sufficiently so that
everyone was let back in.

Incident Response Team members (John, Jim H, Maurice, Gary) determined
that the smell was coming from the wbgen2 bench, near the tylan
oxidation furnaces. Subsequent follow-up determined the following:

1. A labmember was decontaminating labware in the dump rinser.
2. The labmember was using 1:1 concentrated HCl to hydrogen peroxide
(no water).
3. The exhaust on the system was at 0.5" (spec is that the bench should
not be operated when 0.5" or below.)

Normally, decontamination is done using a 5:1:1 ratio of water:HCl:H2O2
or 1:1:1, depending on the need. However, heat of mixing 38% HCl
directly with H2O2 (without sufficient water) results a highly heated
solution -- high enough that there was visible smoke coming from the
dump rinser (remember: hydrogen chloride is a gas at room
temperature). Now, the dump rinser, like most in the lab, is located
slightly in front of the red line behind which exhaust is highest.
During normal operation, the location is not a problem, since cassettes
and wafers to be rinsed carry a limited amount of acid and there is
sufficient exhaust to handle this. However, the dump rinse is clearly
not exhausted well enough to accommodate a gas-generating reaction,
particularly when the exhaust at this station was a hair below spec.

We are determined that this type of incident should NOT happen again.
To ensure this, we will be doing the following:

1. Tightening up our procedures for decontamination of labware and
contaminated stations (to resolve any confusion over appropriate
procedures.)
2. Better establishing the exhaust requirements for each bench (the
current lower limit does not appear to have enough margin for
accidents.) Each station will be audited and there will be
procedural/equipment changes to prevent use with insufficient exhaust.
3. Ensuring that wet bench users are fully aware of these procedures.

If you are a wet bench user, please be prepared for changes in coming weeks.

Thanks for your attention.

Your SNF Staff

--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu

Reminder: CIS/X Building Summer BBQ! (Thursday, 9/11, CISX Patio)

Hi everyone!

Just a reminder of the long overdue CIS/CISX building summer barbecue!
Meet us in the CISX patio tomorrow (Thursday) from 11:30-1 for food,
friends, and fun. Side dishes to share would be appreciated (but
certainly not required.)

Brought to you by our hosts, the CIS Affiliates program (thanks Richard
and Marjorie!)

--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu

Power outage tomorrow morning

SNF Lab Members:

As you may be aware, last Friday we experienced a period of process
chilled water and compressed air failure that was caused by a failure of
one of the electrical panels. We need to shutdown that panel and the
one upstream of it so that the proper circuit breakers can be safely
replaced. The power is scheduled to go off tomorrow (Thursday) morning
at 8 a.m. and should be out for a maximum of 3 hours. We will begin to
power down affected equipment at 6 a.m.

This will likely affect about 25% of the equipment in the lab and will
include:

1. The tools in the little characterization area off the gowning room.
2. The tools along the aisle closest to the gowning room (Rudolph
ellipsometer and other characterization tools.
3. The tools along the aisle with wbgen and sts dep including ALD and
metalica.
4. The tools along the aisle with ASM epi (including the ASM epi burnbox
and scrubber) and stsetch2.
5. AG4100 and AG4108.
6. Innotec.
7. Hitachi Ebeam. We will also be checking whether this will affect any
of the Raith or the sem4160.

Note: This outage will also affect all of the equipment in CIS 152 ....
the private test room where the Cascade probe station, the cryostation,
and a lot of test and circuit work is done.

Note: any tools with cryopumps (ebeam, innotec, metalica and maybe
others) will need a full cryo regen before they are back in operation so
those tools are likely to be down for the full day. Other tools will
likely be operational in the early afternoon.

We apologize for this inconvenience but really can't defer this repair
for long.

Let me know if you have any questions or concerns,

John

Problem p5000etch SNF 2008-09-09 18:56:17: "Can't start with wafer on blade" error

Error comes up when I tried to change the mode to Automatic. Can't process.

Problem p5000etch SNF 2008-09-09 16:00:25: Wafer stuck in Ch. B

For some reason, machine thinks it pulls out the wafer after the process but no wafer came out. the wafer is believed to be inside the chamber.

Comment p5000etch SNF 2008-09-09 10:37:43: Ch.A burnt resist update

Replaced the backside helium lip seal.

Venture Clinic w/Shahin Farschi Tuesday, 3 pm, CIS 101 (today)

Are you thinking about the possibility of building a startup?

Shahin Farshchi, an Associate from Lux Capital, will be moderating a Venture Clinic,
which aims to provide an informal forum for researchers interested in brainstorming
with a venture capitalist on avenues for commercializing technology, what to expect
when starting a new venture.

Technical discussions should be limited to what has been already disclosed or published.

This will take place on Tuesday, Sept. 9 at 3 pm in CIS 101.

For more information, contact:

Shahin Farshchi, Ph.D.
Phone: 925.323.2784
Email: shahin.farshchi@luxcapital.com

--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu

Reminder: Donghun Choi Ph. D Oral Defense, Wednesday, September 10. 10 am (Tomorrow)

 

PhD Thesis Oral Examination

Title:        III-V semiconductor growth on Ge/Si & surface passivation for CMOS technology

Candidate:     Donghun Choi

Advisor:  Prof.  James S. Harris

Time:      10am, Wednesday, September 10, 2008 (refreshments at 9:45am)

Place:     CISX Auditorium

http://campus-map.stanford.edu/index.cfm?ID=04-055

 

Abstract :

 

Integration of III-V compound semiconductors on Silicon substrates has recently received much attention for the development of optoelectronic and high speed electronic devices. However, as is well known, there are some key challenges for the realization of  III-V device fabrication on Si substrates: (i) the large lattice mismatch (in case of GaAs: 4.1%) and (ii) the formation of anti-phase domain (APD) due to the polar compound semiconductor growth on non-polar elemental structure. Besides these growth issues, the lack of a useful surface passivation technology for compound semiconductors has precluded development of metal-oxide-semiconductor (MOS) devices and causes high surface recombination parasitics in scaled devices.

 

This work demonstrates the growth of high quality III-V materials on Si via an intermediate Ge buffer layer, and some surface passivation methods to reduce interface defect density for the fabrication of MOS devices. The initial goal was to achieve both low threading dislocation density (TDD) and low surface roughness on Ge/Si heterostructure growth. This was achieved by repeating a deposition-annealing cycle consisting of low temperature deposition + high temperature-high rate deposition + high temperature hydrogen annealing, using reduced-pressure chemical-vapor-deposition. We then grew III-V materials on these virtual Ge/Si substrates using molecular- beam epitaxy. The relation between initial Ge surface configuration and anti-phase boundary formation was investigated using Ge surface reflection high energy electron diffraction (RHEED) pattern and AFM images analysis. In addition, some MBE growth techniques, such as migration enhanced epitaxy (MEE) and low temperature GaAs growth, were adopted to improve surface roughness and solve Ge self-doping problem. Finally, an Al₂O₃ gate oxide layer was deposited using atomic-layer-deposition system after HCl native oxide etching and ALD in-situ pre-annealing at 400 °C. A 100nm thick aluminum layer was deposited to form the gate contact for a MOS device fabrication. The C-V measurements show very small frequency dispersion and 200-300mV hysteresis, comparable to our best results for InGaAs/GaAs MOS structures on GaAs substrate. Most notably, the quasi-static C-V curve demonstrates clear inversion layer formation. I-V curves show a reasonable leakage current level. The inferred midgap interface state density D_it of 2.4×10¹²cm^-2eV^-1 was calculated by combined high-low frequency capacitance method. In addition, we investigated the interface properties of amorphous LaAlO₃/GaAs MOS capacitors fabricated on GaAs substrate. The surface was protected during sample transfer between III-V and oxide MBD chambers by a thick arsenic-capping layer. An annealing method, a low temperature-short time RTA followed by a high temperature RTA, was developed, yielding extremely small hysteresis (~30 mV), frequency dispersion (~60 mV), and interface trap density (mid 10¹⁰ eV^-1cm^-2). We used capacitance-voltage (C-V) and current-voltage (I-V) measurements for electrical characterization of MOS devices, tapping-mode atomic force microscopy (AFM) for surface morphology analysis, x-ray photoelectron spectroscopy (XPS) for chemical elements analysis of interface, cross section transmission-electron microscopy (TEM), x-ray diffraction (XRD), secondary ion mass spectrometry (SIMS) and photoluminescence (PL) measurement for film quality characterization.

 

This successful growth and appropriate surface treatments of II-V materials provides a first step for the fabrication of III-V optical and electrical devices on the same Si-based electronic circuits.

 

-------------------------------------------------------------------------------------------------------------
  Donghun Choi                                                                                                 
  Ph.D Candidate                                                                                             
                                                                                                                   
  Dep. of Electrical Engineering         Center for Integrated Systerms        
  Prof. James S. Harris group              420 Via Ortega, CIS-X Rm 126x             
  Solid State & Photonics Lab             Stanford, CA 94305                         
  Ph: (650) 725-8313  Fax : (650)  723-4659
  E-Mail:donghun.choi@stanford.edu
  http://snowboard.stanford.edu/~dhchoi                                              
--------------------------------------------------------------------------------------------------------------

Re: Comment p5000etch SNF 2008-07-21 21:47:22: Heat exchanger 0

Archived

Re: Problem p5000etch SNF 2008-09-08 11:00:18: HT EX problem

Reset the heat exchanger.

Re: Comment p5000etch SNF 2008-09-08 13:52:37: Ch. B works fine

Archived

Re: Problem p5000etch SNF 2008-09-05 16:43:52: ht ex error

Reset the heat exchanger.

Comment p5000etch SNF 2008-09-08 13:52:37: Ch. B works fine

Temp has gone down to 14C. It is now ok to use.

Problem p5000etch SNF 2008-09-08 11:00:18: HT EX problem

The cathod temperature is much higher than the set point. I twas around 20C last friday and now is creeping up to 38C.

Compressed Air back on!!!

SNF Lab Members (and folks with other labs depended on Compressed Dry Air):

As of about 9:30 p.m. the compressed air is back on and .... hopefully
.... will stay that way over the weekend. Most tools appear to be
coming back to life without too much fussing .... but please check
carefully for normal operation if you are processing this weekend.

If there seems to be a failure over the weekend, call work control at
x3-2281 .... they should be best able to call the appropriate folks to
deal with this situation.

We apologize for the inconvenience, but hope that you all have a
productive remainder of the weekend.

Happy processing,

John

CSIE 2009, Los Angeles, Papers/Abstracts: September 30

2009 World Congress on Computer Science and Information Engineering
(CSIE 2009)

March 31 - April 2, 2009
Los Angeles/Anaheim, USA

http://world-research-institutes.org/conferences/CSIE/2009

CALL FOR PAPERS, INVITED SESSIONS & EXPO

The Los Angeles/Anaheim area is known for its many renowned
attractions, such as Disneyland, Universal Studios and the
Hollywood Walk of Fame. Very few cities in the world offer
as much entertainment, excitement and diversity as Los
Angeles/Anaheim does.

CSIE 2009 conference proceedings will be published by the IEEE
Computer Society and all papers in the proceedings will be
included in EI Compendex, ISTP, and IEEE Xplore.

CSIE 2009 intends to be a global forum for researchers and
engineers to present and discuss recent advances and new
techniques in computer science and information engineering.
CSIE 2009 consists of the following Technical Symposiums:

* Communications & Mobile Computing Symposium
* Computer Applications Symposium
* Computer Design & VLSI Symposium
* Data Mining & Data Engineering Symposium
* Intelligent Systems Symposium
* Multimedia & Signal Processing Symposium
* Software Engineering Symposium

Invited sessions offer focused discussions on specialized topics.
A prospective invited session organizer should send a proposal,
including a session title, a short synopsis, bio-sketch of the
organizer with a publication list, to the appropriate Symposium
Chair (visit the conference website for more details).

In addition to research papers, CSIE 2009 also seeks exhibitions
of modern products and equipment for computer science and
information engineering.

Important Dates:

Paper/Abstract Submission Deadline: September 30, 2008
Review Notification: November 15, 2008
Final Papers and Author Registration Deadline: December 7, 2008

Organizing Committee:

General Chair:
Adrian Martin, World Research Institutes, USA

Program Chair:
Mark Burgin, University of California at Los Angeles, USA

Symposium Chairs:
Masud H Chowdhury, University of Illinois at Chicago, USA
Chan H. Ham, University of Central Florida, USA
Simone Ludwig, University of Saskatchewan, Canada
Weilian Su, Naval Postgraduate School, USA
Sumanth Yenduri, University of Southern Mississippi, USA

Publicity Chair:
Nitin Upadhyay, Birla Institute of Technology and Science
(BITS), India
David C. Wong, US Environmental Protection Agency, USA

(Please forward to those who may be interested.)

(To unsubscribe all WRI announcements, please reply with the
email subject being "Unsubscribe ALL p5000etch-pcs@snf.stanford.edu".
Thanks and apologies)

(To unsubscribe CSIE announcements only, please reply with the
email subject being "Unsubscribe CSIE p5000etch-pcs@snf.stanford.edu".)

Compressed Air Failure at 5 p.m. ....

SNF Lab Members:

Gaack!!! The Compressed Dry Air (CDA) has just failed and pressure has
dropped to nearly zero.

Unfortunately, this will likely affect many tools. We have called the
facilities off-hours number and Leonard Chan and Jose Solorozano are
being called back to campus. Given that they are likely already on the
roads, it will likely take at least an hour for them to return and then
we'll have to see what the problem is.

Please be on the lookout in there .... I believe that many pieces of
equipment will not be running properly (if at all) at this time.

We'll keep you posted as soon as we know more.

Sorry for the inconvenience,

John

Problem p5000etch SNF 2008-09-05 16:43:52: ht ex error

encounter ht ex error when using chamber B

Lab Utilities OK now

Hi again --

Facilities and John have worked to identify the problem and bring up
utilities in the lab, so we're back in business now. More repairs will
be done on Monday, but these are not expected to affect normal
operations for the most part.

Thanks for your patience (-- and thanks to John and FacOps!)

--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu

Utilities Problem in the Lab

Labmembers --

Facilities informs us that process chilled water and compressed air are
limited or unavailable. This affects most of the equipment in the lab.
The cause is under investigation. We do not have information about when
utilities will be back in service.

Until repairs are made, labmembers are advised not to plan on working in
the lab. Labmembers working in the lab now: please finish what you are
doing but do not start new processing.

Apologies for the inconvenience. We will update you on the status of
the lab as we hear news.

Your Lab Staff

--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu

Problem p5000etch SNF 2008-09-05 15:34:33: Burned resist

Three cases have been reported this week. I looked at one of the wafers and it appears that there might be something on the lip seal. The burning is to one side of the wafer and the user reporrts that the He leak rate is higher than usual....

Problem p5000etch SNF 2008-09-05 15:24:31: CH. A. resist burn, high He leak rate

1.6um 3612 resist with 110C hard bake burned after CH. A Metal recipe. Half of the wafer was burned while half was fine. Nocited Helium leak rate is high.

Chilled water and CDA off ....

SNF Lab Members:

I have just been informed that process chilled water and CDA (compressed
dry air) have just gone off .... and this was not a planned outage.

This means that a number of tools will not work properly, some will have
to be shutdown, and some things will be in danger of overheating.

We will be going around to shutdown those things that we believe need to
be shutdown. Other tools will likely shut themselves down when either
cooling water flow or temperature is too high or when CDA pressure falls.

So .... please process carefully until things have recovered .... it's
very likely that many tools will be affected so please keep your eyes open.

We'll try to keep you informed as soon as we know more ....

Thanks,

John

Process Clinic, Monday, 9/8, 2-4 pm

Hi all --

Next Process Clinic is Monday, 9/8 from 2-4 pm in the cubicle area near
Maureen's office. Bring your process questions, your process flows, and
device layouts. Keith Best from ASML will also be on hand. All
labmembers (and prospective labmembers) are welcome.

Your SNF Staff

--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu

Key Card Access Problems Reported

Dear Labmembers --

If you are having key card problems, it is likely because some key cards
were set to expire on 9/1/08. We have asked the ITSS group to reset
active cards automatically. Until then, please get in touch with
Maureen or John during regular hours and they can help reset your card
manually. Apologies for the inconvenience.

Your Lab Staff

--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu

Donghun Choi Ph. D Oral Defense, Wednesday, September 10. 10 am

 

Title:        III-V semiconductor growth on Ge/Si & surface passivation for CMOS technology

Name:     Donghun Choi

Advisor:  Prof.  James S. Harris

Time:      10am, Wednesday, September 10, 2008 (refreshments at 9:45am)

Place:     CISX Auditorium

 

Abstract :

 

Integration of III-V compound semiconductors on Silicon substrates has recently received much attention for the development of optoelectronic and high speed electronic devices. However, as is well known, there are some key challenges for the realization of  III-V device fabrication on Si substrates: (i) the large lattice mismatch (in case of GaAs: 4.1%) and (ii) the formation of anti-phase domain (APD) due to the polar compound semiconductor growth on non-polar elemental structure. Besides these growth issues, the lack of a useful surface passivation technology for compound semiconductors has precluded development of metal-oxide-semiconductor (MOS) devices and causes high surface recombination parasitics in scaled devices.

 

This work demonstrates the growth of high quality III-V materials on Si via an intermediate Ge buffer layer, and some surface passivation methods to reduce interface defect density for the fabrication of MOS devices. The initial goal was to achieve both low threading dislocation density (TDD) and low surface roughness on Ge/Si heterostructure growth. This was achieved by repeating a deposition-annealing cycle consisting of low temperature deposition + high temperature-high rate deposition + high temperature hydrogen annealing, using reduced-pressure chemical-vapor-deposition. We then grew III-V materials on these virtual Ge/Si substrates using molecular- beam epitaxy. The relation between initial Ge surface configuration and anti-phase boundary formation was investigated using Ge surface reflection high energy electron diffraction (RHEED) pattern and AFM images analysis. In addition, some MBE growth techniques, such as migration enhanced epitaxy (MEE) and low temperature GaAs growth, were adopted to improve surface roughness and solve Ge self-doping problem. Finally, an Al₂O₃ gate oxide layer was deposited using atomic-layer-deposition system after HCl native oxide etching and ALD in-situ pre-annealing at 400 °C. A 100nm thick aluminum layer was deposited to form the gate contact for a MOS device fabrication. The C-V measurements show very small frequency dispersion and 200-300mV hysteresis, comparable to our best results for InGaAs/GaAs MOS structures on GaAs substrate. Most notably, the quasi-static C-V curve demonstrates clear inversion layer formation. I-V curves show a reasonable leakage current level. The inferred midgap interface state density D_it of 2.4×10¹²cm^-2eV^-1 was calculated by combined high-low frequency capacitance method. In addition, we investigated the interface properties of amorphous LaAlO₃/GaAs MOS capacitors fabricated on GaAs substrate. The surface was protected during sample transfer between III-V and oxide MBD chambers by a thick arsenic-capping layer. An annealing method, a low temperature-short time RTA followed by a high temperature RTA, was developed, yielding extremely small hysteresis (~30 mV), frequency dispersion (~60 mV), and interface trap density (mid 10¹⁰ eV^-1cm^-2). We used capacitance-voltage (C-V) and current-voltage (I-V) measurements for electrical characterization of MOS devices, tapping-mode atomic force microscopy (AFM) for surface morphology analysis, x-ray photoelectron spectroscopy (XPS) for chemical elements analysis of interface, cross section transmission-electron microscopy (TEM), x-ray diffraction (XRD), secondary ion mass spectrometry (SIMS) and photoluminescence (PL) measurement for film quality characterization.

 

This successful growth and appropriate surface treatments of II-V materials provides a first step for the fabrication of III-V optical and electrical devices on the same Si-based electronic circuits.

 

-------------------------------------------------------------------------------------------------------------
  Donghun Choi                                                                                                 
  Ph.D Candidate                                                                                             
                                                                                                                   
  Dep. of Electrical Engineering         Center for Integrated Systerms        
  Prof. James S. Harris group              420 Via Ortega, CIS-X Rm 126x             
  Solid State & Photonics Lab             Stanford, CA 94305                         
  Ph: (650) 725-8313  Fax : (650)  723-4659
  E-Mail:donghun.choi@stanford.edu
  http://snowboard.stanford.edu/~dhchoi                                              
--------------------------------------------------------------------------------------------------------------

Camera found outside the lab - Be prepared to describe it

A concerned labmember found a camera outside the lab.  If this is your camera please come by my cubicle #41 and be prepared to describe it. 

 

Maureen

 

Maureen Baran

Stanford Nanofabrication Facility

Lab Services Administrator

mbaran@stanford.edu

650-725-3664

 

End of Summer BBQ: Thursday, 9/11, CISX Patio

To everyone in the CIS/CISX buildings and SNF lab denizens --

Come celebrate the end of summer with a BBQ - next Thursday, September
11, from 11:30-1. There will hamburgers, hot dogs -- and if you're so
inspired, a side-dish to share would be most welcome.

Hope to see you there!

(Brought to you by the CIS Affiliates Program with additional support
from your SNF staff)

--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu

warning from labmembers@snf.stanford.edu

Hi! This is the ezmlm program. I'm managing the
labmembers@snf.stanford.edu mailing list.

I'm working for my owner, who can be reached
at labmembers-owner@snf.stanford.edu.

Messages to you from the labmembers mailing list seem to
have been bouncing. I've attached a copy of the first bounce
message I received.

If this message bounces too, I will send you a probe. If the probe bounces,
I will remove your address from the labmembers mailing list,
without further notice.

I've kept a list of which messages from the labmembers mailing list have
bounced from your address.

Copies of these messages may be in the archive.

To retrieve a set of messages 123-145 (a maximum of 100 per request),
send an empty message to:
<labmembers-get.123_145@snf.stanford.edu>

To receive a subject and author list for the last 100 or so messages,
send an empty message to:
<labmembers-index@snf.stanford.edu>

Here are the message numbers:

3372
3373
3374
3372
3375
3376
3377
3378
3373

--- Enclosed is a copy of the bounce message I received.

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Date: Wed, 20 Aug 2008 23:36:13 -0700 (PDT)
From: MAILER-DAEMON@stanford.edu (Mail Delivery System)
Subject: Delayed Mail (still being retried)
To: labmembers-return-3372-snfblog.P5000=blogger.com@snf.stanford.edu
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