Integration of III-V compound semiconductors on Silicon substrates has recently received much attention for the development of optoelectronic and high speed electronic devices. However, as is well known, there are some key challenges for the realization of III-V device fabrication on Si substrates: (i) the large lattice mismatch (in case of GaAs: 4.1%) and (ii) the formation of anti-phase domain (APD) due to the polar compound semiconductor growth on non-polar elemental structure. Besides these growth issues, the lack of a useful surface passivation technology for compound semiconductors has precluded development of metal-oxide-semiconductor (MOS) devices and causes high surface recombination parasitics in scaled devices.
This work demonstrates the growth of high quality III-V materials on Si via an intermediate Ge buffer layer, and some surface passivation methods to reduce interface defect density for the fabrication of MOS devices. The initial goal was to achieve both low threading dislocation density (TDD) and low surface roughness on Ge/Si heterostructure growth. This was achieved by repeating a deposition-annealing cycle consisting of low temperature deposition + high temperature-high rate deposition + high temperature hydrogen annealing, using reduced-pressure chemical-vapor-deposition. We then grew III-V materials on these virtual Ge/Si substrates using molecular- beam epitaxy. The relation between initial Ge surface configuration and anti-phase boundary formation was investigated using Ge surface reflection high energy electron diffraction (RHEED) pattern and AFM images analysis. In addition, some MBE growth techniques, such as migration enhanced epitaxy (MEE) and low temperature GaAs growth, were adopted to improve surface roughness and solve Ge self-doping problem. Finally, an Al2O3 gate oxide layer was deposited using atomic-layer-deposition system after HCl native oxide etching and ALD in-situ pre-annealing at 400 °C. A 100nm thick aluminum layer was deposited to form the gate contact for a MOS device fabrication. The C-V measurements show very small frequency dispersion and 200-300mV hysteresis, comparable to our best results for InGaAs/GaAs MOS structures on GaAs substrate. Most notably, the quasi-static C-V curve demonstrates clear inversion layer formation. I-V curves show a reasonable leakage current level. The inferred midgap interface state density Dit of 2.4×1012cm-2eV-1 was calculated by combined high-low frequency capacitance method. In addition, we investigated the interface properties of amorphous LaAlO3/GaAs MOS capacitors fabricated on GaAs substrate. The surface was protected during sample transfer between III-V and oxide MBD chambers by a thick arsenic-capping layer. An annealing method, a low temperature-short time RTA followed by a high temperature RTA, was developed, yielding extremely small hysteresis (~30 mV), frequency dispersion (~60 mV), and interface trap density (mid 1010 eV-1cm-2). We used capacitance-voltage (C-V) and current-voltage (I-V) measurements for electrical characterization of MOS devices, tapping-mode atomic force microscopy (AFM) for surface morphology analysis, x-ray photoelectron spectroscopy (XPS) for chemical elements analysis of interface, cross section transmission-electron microscopy (TEM), x-ray diffraction (XRD), secondary ion mass spectrometry (SIMS) and photoluminescence (PL) measurement for film quality characterization.
This successful growth and appropriate surface treatments of II-V materials provides a first step for the fabrication of III-V optical and electrical devices on the same Si-based electronic circuits.
Donghun Choi
Ph.D Candidate
Dep. of Electrical Engineering Center for Integrated Systerms
Prof. James S. Harris group 420 Via Ortega, CIS-X Rm 126x
Solid State & Photonics Lab Stanford, CA 94305
Ph: (650) 725-8313 Fax : (650) 723-4659
E-Mail:donghun.choi@stanford.edu
http://snowboard.stanford.edu/~dhchoi
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