Just wanted to let you know that the Labmembers' Meeting has been
postponed to next Friday, Aug. 8, from 1-2 pm in the CISX Auditorium.
Ed will be back and we should have results to report on the
tylanbpsg/LTO upgrade and qual as well as updates on several other
activities.
Hope to see you there!
Mary
--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu
Dear All,
The actual name of this device is “RSA SecurID”. I’m concerned that someone might be going crazy trying to find it.
Maureen
Maureen Baran
Stanford Nanofabrication Facility
Lab Services Administrator
650-725-3664
From: Maureen Baran [mailto:mbaran@stanford.edu]
Sent: Thursday, July 31, 2008 9:54 AM
To: labmembers@stanford.edu;
Subject: Found Security Token by the Barlett Printer this morning
Dear All,
A Security Token has been found by the
Maureen
Maureen Baran
Stanford Nanofabrication Facility
Lab Services Administrator
650-725-3664
Paul Yick, the ASML site engineer, will be giving a short presentation
about the 3-D align upgrade recently installed and qualified on the ASML
system here at SNF. 3D align, by the way, is a custom feature not
generally available on standard systems and we are fortunate that ASML
has chosen to showcase this capability here.
In brief:
3D-Align is an ASML Enabling Technology that combines Front-side
alignment (FSA) and back-side alignment (BSA). It comprises of a
special 3D-Align exposure table (with embedded optics for wafer
alignment) and the electronics (and software) to route the alignment
signal to the detector.
It is particularly useful for aligning device layers to thick epi, thick
plated metal (in the case of MEMS devices) and color photoresist. It is
cost effective as alignment marks are no longer printed on the
front-side of the wafer & the number of process steps may also be reduced.
Normally, FTFA (Front-to-Front Alignment) is used on critical layers &
BTBA (Back-to-Back Alignment) for non-critical layers. FTBA
(Front-to-Back Alignment) is also a good alternative.
Paul's presentation will be on Wednesday, July 30, at 1 pm in CIS 101.
Your ASML Team
--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu
Does anyone know how to run tsuprem4 on the university unix/linux
machines? I used to be albe to run it a few months ago but now the
program won't start. Any input is appreciated.
Steve
Dear All,
Thank you so much for all your support with the Bake Sale – we sold due to your generosity and Jane’s great baking abilities.
Maybe there will be more bake sales in the future.
Maureen
Maureen Baran
Stanford Nanofabrication Facility
Lab Services Administrator
650-725-3664
Dear All,
Just a Reminder that Jane Edwards is having an AWSOME Bake Sale today. Please come over to Office #141 on the first floor and participate by either buying a treat or donating to the “2008 Breast Cancer 3 Day Walk”. Jane is walking in memory of Maureen Rochford who was an AWESOME friend and admin.
I will be at my desk through the lunch hour so; you can buy a treat to go along with your lunch or afternoon coffee.
Thank you,
Maureen
Maureen Baran
Stanford Nanofabrication Facility
Lab Services Administrator
650-725-3664
Just a reminder that there's a process clinic today, Monday, 7/28, at 2
pm, in the cubicle area near Maureen's office. Keith Best, the
Applications Lab Director at ASML, will be here to field questions as
well. Bring your process flows, bring your processing questions, and
bring your layouts -- and see you this afternoon!
Mary
--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu
Many of you will remember Jane Edwards from when she was our colleague
at SNF. And many of you will remember the wonderful baked goodies she
sold as a fundraiser for the 3-Day Walk for Breast Cancer four years ago.
Jane has decided to do the 2008 Breast Cancer 3-Day Walk in September
benefiting Susan G. Komen for the Cure in memory of Maureen Rochford,
our friend and colleague, who passed away this May.
Last time Jane raised over $4000 and hopes to exceed that for this
year's Walk. She describes the Walk as 'one of those rare occasions
that truly changes your life'.
So please support this cause, honor Maureen R and enjoy some very tasty
cookies, lemon bars and fruit breads by dropping by Maureen Baran's
office (CIS141) on Monday 28 July and purchasing goodies. The sale will
continue until all the treat items are gone.
Thank you for your support,
-Nancy
Just to let you know -- no Grand Rounds (originally scheduled for
Friday, 7/25). Instead, we'll do a roll-up in the Labmembers' Meeting
next Friday, 8/1/08, from 11-12, in the CISX Auditorium. The agenda
will be:
- General announcements
- Quality Circle roll-up
- SNF Project Update
Hope to see you there!
Your SNF Staff
--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu
Two 4" thick quartz rounds which are used as calibration standards for
film stress measurements have been missing for several weeks. They were
last seen next to the FSM stress test system across from Metalica. They
are about one centimeter thick and were kept wrapped in cleanroom
wipes. If you happen to see these in the lab, please let a staff member
know.
By the way, the new Flexus 2320 stress measurement tool is here and is
functional (as far as we can tell, without the reference standards.)
There are no operating procedures as yet and a couple more accessories
need to be ordered, but it is usable. If you'd like to use it, contact me.
Thanks,
Mary
--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu
Dok Won Lee
Department of Materials Science and Engineering
Advisor: Prof. Shan X. Wang
Tomorrow (Friday, July 25th, 2008)
9:00 AM (Refreshments served at 8:45 AM)
CIS-X Auditorium (Rm. 101)
Abstract:
Nowadays cell phones and laptop computers are playing important roles
in our everyday lives, and the demand for more portable electronic
devices continues to increase rapidly. This is currently driving the
integration or embedding of passive components, which would replace
off-chip discrete modular assemblies. However, poor properties of
integrated inductors have been a critical factor limiting the overall
performance of radio-frequency (RF) circuits and hence the realization
of system-on-a-chip (SoC) or system-in-package (SiP) circuits for
portable electronics.
Use of magnetic core with high permeability in the integrated inductor
was proposed decades ago to significantly increase the inductance by
the relative permeability of the magnetic material used. However, the
inductance enhancements reported so far have been limited and not well
explained. In addition, the use of magnetic core comes with the cost
of introducing magnetic power losses. This needs to be well understood
in order to make the magnetic inductor practical and useful.
In this talk, I present the high performance integrated inductors
using a solenoid design with a magnetic layer. A set of analytical
models was developed to describe the device properties of integrated
solenoid inductors. Using the models, design parameters were optimized
to achieve a high inductance while maintaining the lateral device area
< 1 mm^2 and the coil resistance < 1 ohm. The integrated inductors
were fabricated on Si wafers using copper as the conductor layer and
CoTaZr alloy as the magnetic core layer. A polyimide planarization
process was developed as the preceding step for the magnetic core
formation.
The inductance of the fabricated inductor was as high as 70.2 nH
measured at 10 MHz with DC resistance of 0.67 ohm and the device area
of 0.88 mm^2. This is an enhancement by a factor of 34 from the air
core inductor with the identical geometry, and the resulting
inductance density was 80 nH/mm^2. By shrinking the lateral dimensions
while maintaining the vertical dimensions unchanged, the inductance
density further increased to 219 nH/mm^2 without affecting the coil
resistance significantly. The measured device properties and the
calculations using the analytical models show good agreements. The
resistance of the magnetic inductor increased significantly with the
frequency due to the introduction of magnetic power losses at high
frequencies, and the frequency-dependent resistance and quality factor
of the magnetic inductor were also in excellent agreement with the
calculations.
The device properties of the integrated magnetic inductors are well
understood with the analytical models developed and can be further
optimized for applications and frequency ranges of interest. The
integrated magnetic inductors can now be reliably designed and
fabricated for various applications, enabling the realization of the
RF integrated electronics.
--
Dok Won Lee, Ph.D candidate
Materials Science and Engineering, Stanford University
McCullough BLDG Rm.208, 476 Lomita Mall, Stanford, CA 94305-4045
Phone:650-723-4015 | Fax:650-736-1984
I am looking for someway to adhere Au thin film(1um) to Ti substrate without
any glue or tape. One way to do it is sputtering Ti to Au film which will be
extremly time consuming since i need very thick Ti layer. Does anyone have
experience with adhesion of Au to Ti substrate that I can borrow?
All the best,
Ningdong
I use WSxM version 4.0 to process AFM and MFM images. I know version 2.2
is pretty good too. You might find them at www.nanotec.es.
Hope that helps,
Phani.
Arash Hazeghi wrote:
> Hi,
> I am looking for a free GUI software for Windows that can process SPM
> (AFM) RAW images, I have tried a couple so far but they had awkward
> interfaces and bugs. I'd appreciate your recommendations.
>
> Thanks,
> Arash
>
>
>
>
Nanoscale Thin Film Ceramic Fuel Cells
Joon Hyung Shim
Department of Mechanical Engineering
Advisor: Fritz B. Prinz
Wednesday, July 23rd, 2008
10:00AM (Refreshments served @9:45AM)
MERL Conference Room (203)
The ceramic fuel cell (CFC) refers to fuel cells employing solid state ceramic electrolytes, including two types of fuel cells: the solid oxide fuel cell (SOFC) and the proton-conducting oxide fuel cell (PCOFC). Ion conducting ceramics require high operation temperatures of about 700~1000˚C for reasonably active charge transfer reactions at the electrode-electrolyte interface and ion transport through the electrolyte. This high operational temperature has limited CFC applications due to thermal instability of equipped devices. The goal of this study is to minimize Ohmic losses and activation losses at the electrolyte and electrode-electrolyte interface respectively by engineering CFC components to run fuel cells at reduced temperatures.
As a method of engineering SOFC electrolytes, we proposed to fabricate ceramic membranes at the nanometer scale. We have successfully fabricated free-standing 60 nm yttria-stabilized zirconia (YSZ) films, the most common electrolyte material for SOFCs, using atomic layer deposition (ALD). In fuel cell tests with porous platinum electrodes, ALD YSZ showed a maximum power density of 270mW/cm2 at 350˚C, which is a significant improvement from the expected performance estimated from reference values. We found that the performance enhancement originated from an increase in exchange current density at the electrode-electrolyte interface. An oxygen isotope (O18) experiment was used to trace oxide ion diffusion, and it was found that the oxygen-oxide ion exchange rate at the ALD YSZ surface was enhanced compared to the rate in bulk YSZ single crystals, while diffusivity in ALD YSZ films was found to be equal to that of bulk YSZ. This enhancement in the ALD YSZ films was also confirmed in O18 spatial mapping measured by nano-resolution secondary ion mass spectrometry (NanoSIMS).
We have also studied nanoscale yttrium-doped barium zirconate (BYZ) electrolytes as electrolytes for PCOFCs. Thin BYZ films were grown epitaxially on MgO(100) single crystals using pulsed laser deposition (PLD), and conductivity was measured using electrochemical impedance spectroscopy (EIS). X-ray diffraction (XRD) and atomic force microscopy (AFM) data confirmed that BYZ becomes polycrystalline with the formation of grains that negatively affect proton conduction as it grows thicker, and grain growth decreases conductivity by 2~3 times. Freestanding 130nm thick PLD BYZ was tested as an electrolyte in a PCOFC with porous platinum electrodes. A maximum power density of 120mW/cm2 at 450˚C was measured, which is lower than the expected performance based on reference data. This low performance is due to a low exchange current density rooted in low catalytic activity at cathodes. To solve this problem, we performed ALD of BYZ and found that ALD leads to improved quality of the BYZ surface, showing a higher exchange current density and exhibiting an improved maximum power density of 140mW/cm2 at 400˚C. We also confirmed that ALD BYZ fuel cells can operate with methanol as a fuel.
Thanks,
Arash
Bill Martin, representing Compugraphics, will be here to answer your
maskmaking questions. Bring your questions, bring your files. Bill
will be here at 3 pm today. We'll meet in the cubicle area next to
Maureen's office.
Mary
--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu
PhD Thesis Oral Examination
Candidate : Donghyun Kim
Advisor: Prof. Krishna Saraswat
Time : 9:15 am (Refreshments served at 9:00 am)
Date : Thursday, July 24, 2008
Location : CISX-101 Auditorium
Title: Theoretical Performance Evaluations of NMOS Double Gate FETs with
High Mobility Materials : Strained III-V, Ge and Si
Abstract
As Si CMOSFET technology scales down to nanometer scale, it becomes extremely difficult to keep the same drive current due to limitations of channel mobility (µ), gate oxide scaling and parasitics. Currently, strained-Si is the dominant technology for high performance MOSFETs and increasing the strain provides a viable solution to scaling. However, looking into future nanoscale MOSFETs, it becomes important to look at novel channel materials such as strained SixGe(1-x) and strained III-Vs and new device structures.
There are two fundamental problems with these candidates. First, the main advantage of small transport mass to have high injection velocity may be undermined by low density of states which reduces the inversion charge and hence reduces drive current. Second, due to their small effective masses and small band gap combined with high electric fields applied in nanometer-scale devices, large band to band tunneling (BTBT) leakage current is a big concern.
To understand the physics and the performance limitation of nanoscale MOSFETs with high mobility channel materials, we have developed first, a new BTBT model which takes into account complete real and complex band structure, direct/phonon-assisted tunneling, and quantum confinement effect, second, a quantum transport simulator and third, a local pseudo-potential method (LPM) to calculate real and complex band structures of strained semiconductors. While the BTBT models in commercially available TCAD tools largely fail to predict accurate current even in silicon, our model is well matched to experimental results of PIN diodes fabricated on Si, Ge and GaAs, and heterostructure SiGe pMOSFETs.
We have investigated and benchmarked Double-Gate (DG) n-MOSFETs with different channel materials (GaAs, InAs, InSb, Ge and Si). Our results show that with gate oxide thickness of 0.7 nm, small density of states (DOS) of these materials does not significantly limit the on-current (ION) and high µ materials still show higher ION than Si. However, the high µ small bandgap materials like InAs, InSb and Ge, suffer from excessive BTBT current and poor SCE, which limits their scalability. InP has significantly higher ION and shorter intrinsic delay at a reduced IOFF,BTBT when compared to Si.
Strained (uniaxial and biaxial) InxGa1-x As may have a very good tradeoff between the excellent transport properties of InAs and the low leakage of GaAs. Full quantum ballistic simulations with new BTBT models based on the bandstructures calculated by LPM shows that at a l00nA/ µ m Ioff specification, 4% biaxial compressive strained In0.75Ga0.25As (111) NMOS DGFET outperforms other InGaAs compositions because of the excellent transport properties and reduced leakage current with strain engineering.
The power dissipation in nanoscale-MOSFET becomes a huge concern. Reducing VDD is limited by fundamental 60mV/dec turn-off. Band-to Band Tunneling FET (zener mode TFET) is being investigated to overcome 60mV/dec sub-threshold slope, where the transport is dictated by tunneling through a source barrier (instead of diffusion over the barrier). We have experimentally demonstrated a DG, s-Ge, TFET exhibiting record Ion (240uA/um). We have developed a novel quantum transport TFET simulator and our simulations show that the lateral heterostructure is the most scalable approach to solving the ambipolar problem in TFETs.
Is there anyone who did SiO2 sputtering before? I am developing my
process for sputtered ~10 nm SiO2. I am concerning the roughness and
density of the film. I would like to get advice if some labmembers
have previous experience. Thanks.
Yoonyoung
--
Yoonyoung Chung
Ph.D. Candidate
Department of Electrical Engineering
Stanford University
Email: yoonyoung.chung@stanford.edu
---------------------------------------------------------
Final judge is by Nature itself
Dok Won Lee
Department of Materials Science and Engineering
Advisor: Prof. Shan X. Wang
Friday, July 25th, 2008
9:00 AM (Refreshments served at 8:45 AM)
CIS-X Auditorium
Abstract:
Nowadays cell phones and laptop computers are playing important roles
in our everyday lives, and the demand for more portable electronic
devices continues to increase rapidly. This is currently driving the
integration or embedding of passive components, which would replace
off-chip discrete modular assemblies. However, poor properties of
integrated inductors have been a critical factor limiting the overall
performance of radio-frequency (RF) circuits and hence the realization
of system-on-a-chip (SoC) or system-in-package (SiP) circuits for
portable electronics.
Use of magnetic core with high permeability in the integrated inductor
was proposed decades ago to significantly increase the inductance by
the relative permeability of the magnetic material used. However, the
inductance enhancements reported so far have been limited and not well
explained. In addition, the use of magnetic core comes with the cost
of introducing magnetic power losses. This needs to be well understood
in order to make the magnetic inductor practical and useful.
In this talk, I present the high performance integrated inductors
using a solenoid design with a magnetic layer. A set of analytical
models was developed to describe the device properties of integrated
solenoid inductors. Using the models, design parameters were optimized
to achieve a high inductance while maintaining the lateral device area
< 1 mm^2 and the coil resistance < 1 ohm. The integrated inductors
were fabricated on Si wafers using copper as the conductor layer and
CoTaZr alloy as the magnetic core layer. A polyimide planarization
process was developed as the preceding step for the magnetic core
formation.
The inductance of the fabricated inductor was as high as 70.2 nH
measured at 10 MHz with DC resistance of 0.67 ohm and the device area
of 0.88 mm^2. This is an enhancement by a factor of 34 from the air
core inductor with the identical geometry, and the resulting
inductance density was 80 nH/mm^2. By shrinking the lateral dimensions
while maintaining the vertical dimensions unchanged, the inductance
density further increased to 219 nH/mm^2 without affecting the coil
resistance significantly. The measured device properties and the
calculations using the analytical models show good agreements. The
resistance of the magnetic inductor increased significantly with the
frequency due to the introduction of magnetic power losses at high
frequencies, and the frequency-dependent resistance and quality factor
of the magnetic inductor were also in excellent agreement with the
calculations.
The device properties of the integrated magnetic inductors are well
understood with the analytical models developed and can be further
optimized for applications and frequency ranges of interest. The
integrated magnetic inductors can now be reliably designed and
fabricated for various applications, enabling the realization of the
RF integrated electronics.
--
Dok Won Lee, Ph.D candidate
Materials Science and Engineering, Stanford University
McCullough BLDG Rm.208, 476 Lomita Mall, Stanford, CA 94305-4045
Phone:650-723-4015 | Fax:650-736-1984
We are looking to try out a copper etchant before buying some ourselves.
If you use any kind of copper etchant and have a few mL that you would
be willing to give us, we would be very grateful.
-Kathryn
A cell phone was left in the gowning room a short time ago. If you are missing your phone please come by my cubicle (# 41) on the first floor and pick it up.
Maureen
Maureen Baran
Stanford Nanofabrication Facility
Lab Services Administrator
650-725-3664
Nanoscale Thin Film Ceramic Fuel Cells
Joon Hyung Shim
Department of Mechanical Engineering
Advisor: Fritz B. Prinz
Wednesday, July 23rd, 2008
10:00AM (Refreshments served @9:45AM)
MERL Conference Room (203)
The ceramic fuel cell (CFC) refers to fuel cells employing solid state ceramic electrolytes, including two types of fuel cells: the solid oxide fuel cell (SOFC) and the proton-conducting oxide fuel cell (PCOFC). Ion conducting ceramics require high operation temperatures of about 700~1000˚C for reasonably active charge transfer reactions at the electrode-electrolyte interface and ion transport through the electrolyte. This high operational temperature has limited CFC applications due to thermal instability of equipped devices. The goal of this study is to minimize Ohmic losses and activation losses at the electrolyte and electrode-electrolyte interface respectively by engineering CFC components to run fuel cells at reduced temperatures.
As a method of engineering SOFC electrolytes, we proposed to fabricate ceramic membranes at the nanometer scale. We have successfully fabricated free-standing 60 nm yttria-stabilized zirconia (YSZ) films, the most common electrolyte material for SOFCs, using atomic layer deposition (ALD). In fuel cell tests with porous platinum electrodes, ALD YSZ showed a maximum power density of 270mW/cm2 at 350˚C, which is a significant improvement from the expected performance estimated from reference values. We found that the performance enhancement originated from an increase in exchange current density at the electrode-electrolyte interface. An oxygen isotope (O18) experiment was used to trace oxide ion diffusion, and it was found that the oxygen-oxide ion exchange rate at the ALD YSZ surface was enhanced compared to the rate in bulk YSZ single crystals, while diffusivity in ALD YSZ films was found to be equal to that of bulk YSZ. This enhancement in the ALD YSZ films was also confirmed in O18 spatial mapping measured by nano-resolution secondary ion mass spectrometry (NanoSIMS).
We have also studied nanoscale yttrium-doped barium zirconate (BYZ) electrolytes as electrolytes for PCOFCs. Thin BYZ films were grown epitaxially on MgO(100) single crystals using pulsed laser deposition (PLD), and conductivity was measured using electrochemical impedance spectroscopy (EIS). X-ray diffraction (XRD) and atomic force microscopy (AFM) data confirmed that BYZ becomes polycrystalline with the formation of grains that negatively affect proton conduction as it grows thicker, and grain growth decreases conductivity by 2~3 times. Freestanding 130nm thick PLD BYZ was tested as an electrolyte in a PCOFC with porous platinum electrodes. A maximum power density of 120mW/cm2 at 450˚C was measured, which is lower than the expected performance based on reference data. This low performance is due to a low exchange current density rooted in low catalytic activity at cathodes. To solve this problem, we performed ALD of BYZ and found that ALD leads to improved quality of the BYZ surface, showing a higher exchange current density and exhibiting an improved maximum power density of 140mW/cm2 at 400˚C. We also confirmed that ALD BYZ fuel cells can operate with methanol as a fuel.
For those of you who missed the last Labmembers' meeting, slides and
info have been posted (link on the SNF home page.) Also, summaries of
various quality circle meetings have been posted as well. The next
Process Grand Rounds will be on Friday, July 25, at 11:30 am in CIS
101. The next Labmembers' Meeting will be on Friday, August 1, from
11-12 in the CISX Auditorium.
Just a reminder: all labmembers are welcome to attend, participate, and
contribute.
Your SNF Staff
--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu
The Environmental Protection Agency ( EPA) began regulating the use
of *Perfluoroalkyl sulfonates * and more specific to us,
perfluorooctyl sulfonates. What does all this mean? Roham & Hass (
Shipley) will not make or deliver any Ldd26W ( our developer) that we
use with 3612 resist which contain this chemical by *January of 2009.*
This means that December will be the last of the shipment of the developer.
I like to switch even earlier if would be possible.
I have started running experiment with other developers and that will
take some time for me. I am running the process side by side and then do
SEM and then repeat it one more time to prove that all is under control.
*I have created a recipe #8 on SVGDEV2 for me please leave it
alone so I do not have to program it every time.
*
I am trying to do this as efficiently and quickly as possible and
share the information with you so you have enough time to confirm the
change for yourself . I am sure that the change will most likely be
transparent to your process.
The dead line I have given my self would be till September and if all
goes well then you will have enough time to confirm that for your self
if you choose to.
If you have concerns/suggestions or have some extra time that you can
put toward community service, let Mary or I know and we will put that
toward a good use.
My apology for sending out duplicate emails.
mahnaz
Thanks,
Jason
SNF staff will be on hand today, from 2-4 pm, for the biweekly process
clinic. Bring your process questions, runsheets, and mask layouts.
Senior labmembers are also welcome to offer expertise.
Your SNF Staff
--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu
-- Candace K. Chan Ph.D. Student, Department of Chemistry Stanford University McCullough Building Room 209 476 Lomita Mall Stanford, CA 94305
The fab is recovering from a short power glitch late this
afternoon. Most of the tools have been restarted, but we are waiting
on some of the metal deposition cryo's to recover and the ASML. In
addition the burn box for the ASM epi and STS PECVD are still in fault.
Please review comments in Coral before running any of the tools. The
tool you want may be fine, waiting for recovery or down until further notice.
Sorry for the interruption,
SNF Staff
Furnaces (tylan 1-12, but thermco is fine), epi (1 and 2), and RTA
(Ag4100 and 4108) were suddenly turned off at around 4:30pm on Sat.
Jin-Hong
--
JinHong Park (Ph.D. Candidate)
Department of Electrical Engineering, Stanford University
Cubicle 45, B113, Center for Integrated Systems(CISX),
420 Via Palou, Stanford, California, 94305
Dr. Bo Pi, from Nanolithography Solutions, will be here to talk about
his company's technology on Monday, July 14, at 2 pm in the CISX
Auditorium. Nanolitho Solutions has licensed HP's nanoimprint
technology and is looking for researchers to partner with. The system
consists of a module that fits into a standard contact aligner, such as
the ones at SNF.
For more information about Nanolitho Solutions:
http://www.eetimes.com/showArticle.jhtml;jsessionid=A2OEDSFKZN0OAQSNDLPCKHSCJUNN2JVN?articleID=199902421
--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu
Organic semiconductors for flexible electronics
July 11, 1:30-2:30CISX-Auditorium Henning Sirringhaus
Professor, Cambridge University , UK Chief Scientist, PlasticLogic Conjugated polymer semiconductors offer new opportunities for the controlledmanufacturing of active electronic circuits by a combination of solutionprocessing and direct printing. We will review current understanding oftheir device physics with a particular emphasis on understanding theelectronic structure of polymer heterointerfaces governing the deviceperformance. Recent advances include realization of ambipolar organictransistors which allow easy integration of information processing andlight-emission functions. We will also review recent progress towardsmanufacturing of organic transistor circuits by high-resolution printingtechniques for applications in displays and low-cost intelligent labels.
Henning Sirringhaus is the Hitachi Professor of Electron Device Physics at the Cavendish Laboratory. He has been working in the field of organic transistor devices since 1997. He has an undergraduate and PhD degree in physics from ETH Zürich (CH). From 1995-1996 he worked as a postdoctoral research fellow at Princeton University (USA) on a-Si TFTs for active-matrix liquid crystal displays. He is co-founder and Chief Scientist of Plastic Logic Ltd., a technology start-up company commercialising printed organic transistor technology. He was awarded the Mullard award of the Royal Society in 2003. His scientific interests include the charge transport physics of molecular, and polymeric semiconductors, the development of printing-based nanopatterning techniques, and the use of scanning probe techniques for electrical characterization of functional nanostructures.
As the Deputy Director of Stanford's Center for Probing the Nanoscale,
an NSF-funded Nanoscale Science and Engineering Center (NSEC), I would
like to bring to your attention an opening for Associate Director of our
Center.
We are seeking a full-time Associate Director for the new Center for Probing
the Nanoscale (CPN), an NSF-funded Nanoscale Science and Engineering Center
(NSEC). The Associate Director will evolve, direct, and evaluate CPN's
educational and industrial programs and partnerships; manage the day-to-day
educational and outreach activities of the Center; monitor scientific
operations; and work with Center PIs on stewardship of the core grant and
on seeking new funding opportunities. The Associate Director will be one of
two full-time staff members and, along with the Program
Administrator/Financial Analyst, will be responsible for monitoring
operations and will report to the Director. The successful candidate will
be able to explain concepts in physical science to both nonexperts and
experts, and will have, or be interested in acquiring, knowledge of
nanoscale science and technology. A PhD in a science or engineering field
is highly desired, but exceptional candidates with a Master's or Bachelor's
will be considered. Experience with education at the K-12 or
community college level is also highly desired, especially work on
curriculum or assessment of educational programs. The successful
candidate will help to set the directions and priorities of the Center.
The position requires demonstrated outstanding communication and
organizational skills; the ability to set priorities and enact them in a
fluid and fast-paced environment; and, above all, a passion to facilitate
learning and share the joy of science and technology.
To apply, please go to the Stanford Careers website,
http://jobs.stanford.edu, and search for position # 31176, where you can
find a somewhat more detailed description of the Associate Director
position (just posted today, July 10, 2008). You will be
asked to submit a CV and cover letter. In your letter, please indicate how
you heard about this position. If you have questions, please contact
Laraine Lietz-Lucas, Program Administrator of CPN, at lietz@stanford.edu.
We will begin screening applications July 21st, and will continue until
we have filled the position. While we are eager to get an Associate
Director in place soon, we are even more keen to find an outstanding
partner to work with for years to come.
Best wishes,
David
----------------------------------------------------------------------------
David Goldhaber-Gordon
goldhaber-gordon@stanford.edu
Assistant Professor of Physics davidg@post.harvard.edu
Stanford University (permanent forwarding)
www.goldhaber-gordon.com
(650) 725-2047 (lab) (650) 724-3709 (office)
Address for letters or packages: Administrative Associate:
David Goldhaber-Gordon Roberta Edwards
Geballe Laboratory for Advanced Materials McCullough, Rm. 338
McCullough Building, Room 346 Phone: (650) 723-8028
476 Lomita Mall Fax: (650) 724-3681
Stanford, CA 94305-4045 email: redward@stanford.edu
Shahin Farschi, an Associate from Lux Capital, will be moderating a Venture Clinic.
This will be Thursday, July 10, at 2 pm in CIS 101. The aim of the clinic is to provide
an
informal forum for researchers interested in brainstorming with a venture capitalist
on ways to commercialize research. Technical discussions should be limited to what
has been already disclosed or published.
For more information, contact:
Shahin Farshchi, Ph.D.
Associate
Lux Capital Management, LLC
T: 925.323.2784
http://www.luxcapital.com
Bill Martin, our itinerate maskmaking expert, will be dropping by at 2
pm today. If you have any maskmaking questions, he'll be available to
answer them. We'll be in the cubicle area by CIS 41.
M
--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu
Organic semiconductors for flexible electronics
July 11, 1:30-2:30CISX-Auditorium Henning Sirringhaus
Professor, Cambridge University , UK Chief Scientist, PlasticLogic Conjugated polymer semiconductors offer new opportunities for the controlledmanufacturing of active electronic circuits by a combination of solutionprocessing and direct printing. We will review current understanding oftheir device physics with a particular emphasis on understanding theelectronic structure of polymer heterointerfaces governing the deviceperformance. Recent advances include realization of ambipolar organictransistors which allow easy integration of information processing andlight-emission functions. We will also review recent progress towardsmanufacturing of organic transistor circuits by high-resolution printingtechniques for applications in displays and low-cost intelligent labels.
Henning Sirringhaus is the Hitachi Professor of Electron Device Physics at the Cavendish Laboratory. He has been working in the field of organic transistor devices since 1997. He has an undergraduate and PhD degree in physics from ETH Zürich (CH). From 1995-1996 he worked as a postdoctoral research fellow at Princeton University (USA) on a-Si TFTs for active-matrix liquid crystal displays. He is co-founder and Chief Scientist of Plastic Logic Ltd., a technology start-up company commercialising printed organic transistor technology. He was awarded the Mullard award of the Royal Society in 2003. His scientific interests include the charge transport physics of molecular, and polymeric semiconductors, the development of printing-based nanopatterning techniques, and the use of scanning probe techniques for electrical characterization of functional nanostructures.
Thanks,
Jason
With deepest apologies for the mixup last time, we're please to another visit with Shahin Farschi:
Are you thinking about starting a company to commercialize your research?
Shahin Farschi, an Associate from Lux Capital, will be moderating a Venture Clinic.
This will be Thursday, July 10, at 2 pm in CIS 101. The aim of the clinic is to provide an
informal forum for researchers interested in brainstorming with a venture capitalist
on ways to commercialize research. Technical discussions should be limited to what
has been already disclosed or published.
For more information, contact:
Shahin Farshchi, Ph.D.
Associate
Lux Capital Management, LLC
T: 925.323.2784
http://www.luxcapital.com
--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu
A colleague, Erik Shirokoff, has done a lot of wafer bonding research.
He is currently using spun-on BCB, I believe.
-Kam
On Mon, Jun 30, 2008 at 11:40 PM, ben.jian
<ben.jian@arrayedfiberoptics.com> wrote:
> Dear labmembers,
>
> I have been doing silicon-silicon wafer bonding for years using gold-silicon
> eutectic bonding. While this is a reasonable wafer bonding method, it
> leaves much to be desired. Briefly, the bond is not very strong -
> frequently even ultrasonic cleaning can break the bonded chip stack.
>
> I am looking for a better silicon-silicon wafer bonding process. Factors to
> consider include process simplicity, bonding yield/strength, tolerance to
> dust particle, etc. If every step can be performed at SNF, it would be
> always better. A lower temperature process is desirable.
>
> Your kind advice is greatly appreciated.
>
> Ben Jian
>
>
--
Kam Arnold
Graduate Student Researcher
UC Berkeley Physics Department
351 LeConte Hall
Berkeley, CA 94720-7300
Office: 1 510 643 8161
Fax: 1 510 643 5204