ME PhD Dissertation Defense: Rebecca Taylor (Thursday, Nov 8th at 8:00am)

University PhD Dissertation Defense

Microfabricated tools for functional assessment of developing cardiomyocytes

Rebecca Taylor

Advisors: Prof. Beth L. Pruitt and Prof. Ellen Kuhl

Department of Mechanical Engineering, Mechanics and Computation Division, Stanford University

Thursday, November 8th, 2012 at 8:00am (Refreshments at 7:45am)

Location:  Mitchell Earth Sciences Building, Hartley Conference Room 130

http://campus-map.stanford.edu/?id=04-560&lat=37.4264170549&lng=-122.172654692&zoom=17&srch=Mitchell (Ruth Wattis)

Abstract:

      Ischemic damage following myocardial infarction often leads to heart failure, contributing to cardiovascular disease's status as the number one killer in developed countries. This year an estimated 785,000 people in the United States alone will have their first heart attack. This underscores the critical need for cardiac therapies to actively repair damaged tissue. These therapies will be predicated upon knowledge of the mechanisms of cardiac growth and disease, including the development of contractile function and electrophysiological properties in maturing heart cells. 

      Two major barriers to this work involve the lack of tools for direct functional assessment for developing cardiomyocytes: (1) Axial force generation can not be assessed using current platforms and imaging techniques. (2) While cardiomyocyte phenotype and twitch power are improved when these cells are cultured on soft, tissue-like substrates in the 10-15 kPa range, standard in vitromicroelectrode arrays can not be used to study electrophysiology with cells cultured on soft, stretchable substrates. To address these issues, two different classes of device were microfabricated to perform direct functional assessment of developing cardiomyocytes.

      A sacrificial layer technique was developed to suspend immature cardiomyocytes across pairs of widely-separated elastomer microposts.  By prescribing a physiological cell shape and two-point loading, purely axial measurements of force generation were made during cardiomyocyte contraction.  This force post technique achieved unmatched accuracy and precision, because microposts were directly calibrated using piezoresistive cantilevers of known stiffness, and in this measurement uncertainty was shown to be less than biological variation, a critical achievement for an elastomer technique.  Forces of up to 146 nanoNewtons were measured.  These forces were much smaller than the microNewton-scale forces reported from adult cardiomyocytes, suggesting that force generation capacity may increase with cardiomyocyte development.  This technique provides a window into the development biology of healthy cardiomyocytes and a means to study the cardiac disease progression that was previously impossible.

      In addition, to address the need for electrophysiological characterization of cardiomyocytes grown on soft, stretchable substrates, two different approaches were used to fabricate stretchable microelectrode arrays (SMEAs). A microfluidic platform filled with conductive ink and a flex circuit-based SMEA with a novel geometry were created.  Both SMEAs maintain planarity and electrical properties throughout cyclic strains of up to 15%, and enable electrophysiological study of heart cells grown in biomimetic, soft and stretching environments.

      Microfabrication has been used to develop devices for directly assessing cardiomyocyte function.  These platforms overcome critical challenges to the handling, manipulation, and culture of immature cardiomyocytes, and are relevant for translational research as well as basic developmental and physiological investigations of stem cell-derived cardiomyocytes.

Rebecca Taylor 

Bio-X and DARE Fellow
Graduate Research Assistant
Microsystems & Biomechanical Computation Groups
Mechanical Engineering
Stanford University

Seminar on Semiconductor Packaging and 3D ICs

Semiconductor Packaging and 3D ICs

Speaker: Jan Vardaman, Founder and President, Techsearch

Time: 4:15-5:30pm

Date : Wednesday, 10/31/2012 @ CIS-X 101

Abstract
In the last decade, advanced packaging has emerged as an enabler of today's electronic products. The impact of packaging, assembly, and test is increasingly felt in the semiconductor industry and package selection is important to the success of the end product.

While the drivers for 3D ICs remain performance and form factor, the time line for its adoption keeps shifting out into the future. Several technical challenges and infrastructure issues such as business logistics are delaying the full commercialization of TSV technology for 3D ICs. Until these issues can be resolved, alternative packages will be the choice for high volume manufacturing. Once the 3D IC technical challenges are resolved and the technology becomes cost-effective, business challenges will remain until the industry settles on a model.

This presentation provides an introduction into trends in semiconductor packaging and insight into technology and business challenges in the adoption of new technologies.

Speaker Bio
E. Jan Vardaman is president and founder of TechSearch International, Inc., which has provided analysis on technology and market trends in semiconductor packaging since 1987. She is co-author of How to Make IC Packages (published in Japanese by Nikkan Kogyo Shinbunsha), a columnist with Circuits Assembly Magazine, and the author of numerous publications on microelectronics market and technology trends. TechSearch International has published detailed analysis of the business and technology issues in the adoption of 3D ICs. She is a member of IEEE CPMT, IMAPS, IPC, MEPTEC, and SEMI. She was elected to two terms on the IEEE CPMT Board of Governors. Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry's first pre-competitive research consortium.

Re: Al2O3 etching

Max,

Back in 2006 with ALD A2O3 from our modified Spectrum CVD system, we used the following recipe in the P5000.

(BCl3=40/Cl2=10/N2=40/200mT/300W/0G).

cleared about 200A of ALD-Al2O3 in 45 seconds (266A/min).

Jim

----- Original Message -----
From: "Max Marcel Shulaker" <maxms@stanford.edu>
To: "labmembers" <labmembers@snf.stanford.edu>
Sent: Tuesday, October 30, 2012 1:25:48 PM
Subject: Al2O3 etching

Hello everyone,
Hope it's a happy tuesday for you. I was wondering if someone had experience dry etching Al2O3 from a fiji ALD chamber? I have some recipes, but am wondering what other people use and what etch rates they get, etc. Right now, I use BCL3/Cl2 on pquest, but am worried about the chloride and nasty residues left behind...
Thanks!
-Max

SNF tool interruption this morning in aisle 109 and proximity.

SNF users,

We interrupted processing to resolve an electrical safety issue.  Our apologies for the inconvenience but the picture below is worth a thousand words and possible a call to the fire department eventually.  

This white ground was removed, replaced and more securely attached.

I want to thank Jim Haydon for his efforts coordinating and the user base for your patience.  

Brett E. Huff

SNF Clean Room Manager

Stanford University

©510-612-8670

bhuff@stanford.edu

Al2O3 etching

Hello everyone,
Hope it's a happy tuesday for you. I was wondering if someone had experience dry etching Al2O3 from a fiji ALD chamber? I have some recipes, but am wondering what other people use and what etch rates they get, etc. Right now, I use BCL3/Cl2 on pquest, but am worried about the chloride and nasty residues left behind...
Thanks!
-Max

MSE PhD Dissertation Defense: Don koun Lee (Fri, November 9th, 10AM)

Department of Materials Science & Engineering

University PhD Dissertation Defense 

 

Nano-fabrication and Characterization of emerging memory technology specialized in spintronics

 

Don Koun Lee

Advisor: Prof. Shan X. Wang

 

Date: Friday, November 9th, 2012

Time: 10:00 AM (Refreshment served at 09:45 AM)

 

Location: Spilker Building (Center for Nanoscale Science and Engineering, Nano building)

Conference room # 232

 

Abstract

First part: Spin transfer torque (STT) devices with a nano aperture

Recent progresses in spin transfer torque (STT)-based random access memory make it a realistic contender in the race toward next generation solid state data storage devices. However, the relentless scaling-down of device dimensions stemming from the Moore's law mandates that the STT-based devices have a spin switching current density of well below 10⁶ A/cm² while maintaing thermal stability of data bits stored, which are usually two contradictory requirements that have spurred worldwide research for new approaches to boost STT with minimal spin currents. We demonstrate that a reduction of the switching current by a factor of >100 in a magnetic tunnel junction (MTJ) pillar of 200 × 400 nm² can be achieved with a nano-aperture of 30 × 30 nm². In the presence of the nano-aperture, there is a large component of current in the plane of the free layer that creates the adiabatic and non-adiabatic spin torques on the free layer in addition to the conventional spin torque of the tunnel current. A micromagnetic simulation including these competing spin torques confirms that the in-plane current induced spin torques generate spin waves that causes the dramatic reduction of the tunnel current required for switching. The nano-apertured MTJ pillars presented in this work provide a promising path to the large scale practical applications of STT devices since they retain their thermal stability over 10 years and simultaneously achieve a low switching tunnel current of the order of 10⁴ A/cm².

 

Second part: Low contact resistance in Ge/MgO/CoFeB spin diodes

While the rapid and continued progress in the scalability and the integration technology of conventional planar transistor facing the physical limitation, introduction of the new functionality into the transistors has emerged as one of the alternative approaches for the future integrated electronics technology. One of the current issues for improving the efficiency of the spin injection from the ferromagnetic materials (FM) into semiconductors (S) is the conductivity mismatch between both materials because the spin injection can be greatly affected by the ratio of both conductivities. Recent reports suggested that the improvement in the spin injection could be achieved by an ultra thin oxide layer between FM and S. In addition, the oxide barrier also reduces the metal-induced gap-state (MIGS) density at the interface between FM and S, which can release the Fermi level pinning and decrease the effective barrier height. We studied and compared the Schottky barrier height of FM/S and FM/oxide/S and demonstrated that the ultra thin oxide layer between FM and S can modulate the effective barrier height based on measurement of the current versus voltage characteristics and a thermionic emission model. Moreover, we will discuss how contact resistance of spin diodes can be optimized by fine control of MgO layer thickness. 

Don Koun Lee 
Ph.D. Candidate 
Materials Science and Engineering 
Stanford University

Oral Exam Announcement: Gary Shambat

Ph.D. Dissertation Defense for Gary Shambat

Title:

From solid state to soft matter: 

Photonic nanocavities as advanced optoelectronic devices and single-cell biomedical probes

Advisor: Professor Jelena Vučković

Department of Electrical Engineering

 

Thursday, November 8^th 2012

10:00 AM

(Refreshments at 9:45 AM)

 

Location: Clark Auditorium (outside entrance at the very center of Clark building)

 

 

Abstract:

 

Photonic nanocavities are wavelength-scale dielectric structures that possess remarkable properties due to their intrinsic small sizes and high quality factors. Simply by modifying the device materials and optical properties, one can realize nanocavities for diverse applications ranging from lasers to quantum optics and even biosensing. In this talk I will present two drastically different functions of nanocavities, both of which make them more practical for real-world adoption.   

 

The first half of my presentation will focus on how photonic crystal (PC) cavities can be utilized for ultra-low energy and ultra-fast optical sources for next-generation communications. To date, the true power of these nanocavities has only been demonstrated by using secondary optical control, preventing realistic integration of devices with electronics. We have therefore developed a new platform for efficiently driving PC cavities using a lithographically defined, lateral p-i-n junction. With our lateral junction we have demonstrated a world record low threshold laser with a threshold power of only 208 nW at 50K. At room temperature we find that these same devices behave as ultra-fast light-emitting diodes which can be directly modulated at up to 10 GHz. Additional active photonic devices incorporating a lateral junction will also be discussed.

 

The second half of my talk describes the demonstration of a whole new class of tools that marry PC cavities to the tips of optical fibers. The form factor of the optical fiber lends itself to operation of the tool in exotic environments never before accessible to a nanocavity. Specifically we have used our probes to interrogate single human prostate cells with internalized PC cavities showing, for the first time, resonant photonic modes inside biological cells. The beams can be loaded in cells and tracked for days at a time, with cells undergoing regular division and migration. Furthermore, we present in vitro label-free protein sensing with our probes as a path towards quantitative, real-time biomarker detection in single cells.

NNIN ALD roadshow returns home (November 1st)

Hello fellow SNF labmembers,

Michelle Rincon and I have had the opportunity to travel to a few of the other NNIN sites recently to discuss and share information about ALD.  this has gone a long way toward improving the interactions between the universities on this topic and hopefully will lead to further interplay in the network going forward.

when visiting the schools, i have given a couple of talks to the users at those sites:

talk 1:  introduction to ald (meant to start from no familiarity with ald and get you up to speed with the process and some of the intricacies)

talk 2:  a deeper dive into ald (more advanced look at ald, metrology, recipe characterization, etc)

i believe these talks and the subsequent Q&A that can come from them maybe very useful to the snf users.  even if you are already trained on ald tools in the snf, both talks will have points you may not know.  plus i can share some of the things learned from other sites (this will come in talk 2).

so here is the schedule:

November 1, 2012, in Allen 101

11:00-12:30 Introduction to ALD Theory and Practice

1:30 - 3:00  A Deeper Dive Into ALD

I hope of you are interested can attend.

J

Laminar hood problem in SNF Litho Update

Facilities is reporting that the transfer fan above the ASML/Yes Oven may be down overnight. The other fan in that aisle is back up and running at 100%.

If you need to work on sensitive processes in that area you may want to wait until the fan in that area is back up.

We will send another update once we have more information.


-m


On Oct 25, 2012, at 12:00 PM, Mary Tang <mtang@stanford.edu> wrote:

> Dear labmembers --
>
> We've just been informed that two air transfer fans have failed so that there is no laminar flow in part of the Litho area. Facilities is working on a temporary repair which they expect will be done around 2 pm today. The laminar flow hoods affected are the ones that serve L101 aisle (Karlsuss1/2, lithosolv, ASML) and L100 (ovens, YES, headway2.)
>
> The litho area will remain open. However, we advise that if you have any defect sensitive processes, you may want to delay work until the laminar flow is back on later today.
>
> Please also note that when the laminar flow comes back on later today, it will be at 100% capacity rather than scaled back to 2/3 as it runs in the rest of the lab and the L102 aisle (SVGcoat, SVGdev, EValign systems). This will no doubt be louder and may result in odd air flow patterns in the litho area. Facilities has ordered parts for repair, but do not yet have an estimate as to when the parts are due in and repairs can take place. We will update you as soon as we hear.
>
> Thanks for your attention --
>
> Your SNF Staff
>
>
>
> --
> Mary X. Tang, Ph.D.
> Stanford Nanofabrication Facility
> Paul G. Allen Room 136, Mail Code 4070
> Stanford, CA 94305
> (650)723-9980
> mtang@stanford.edu
> http://snf.stanford.edu
>

2012 NNIN ALD Workshop - Registration Open

Hello all,

I wanted to let you know about the NNIN ALD workshop that is being organized by Stanford, Cornell, and Harvard.  The workshop will be held at Harvard right after MRS Boston.  It should be a great opportunity to talk ALD.  Please feel free to ask me any questions about registration.

Best,

Michelle

---------------------------------------------

Michelle Rincon, PhD
Process Staff Engineer
Stanford Nanofabrication Facility

(650)-725-0307
mmrincon@stanford.edu

Begin forwarded message:

From: Mac Hathaway <hathaway@cns.fas.harvard.edu>

Subject: 2012 NNIN ALD Workshop - Registration Open

Date: October 24, 2012 2:05:06 PM PDT

To: Parag Banergee <parag.banergee@wustl.edu>, Michael Khbeis <khbeis@uw.edu>, Kate Nelson <nelsonk@seas.wustl.edu>, Gary Harris <gharris@msrce.howard.edu>, Trevor Thornton <t.thornton@asu.edu>, Arthur Handugan <handugan@asu.edu>, Michelle Rincon <mmrincon@snf.stanford.edu>, Vincent Genova <Genova@cnf.cornell.edu>, "de Rouffignac, Philippe" <philippe@cns.fas.harvard.edu>

Hello All,

This is Mac Hathaway, at the Harvard Center for Nanoscale Systems.  I'm writing today to let you know about the 2012 NNIN ALD Symposium, to be held on Nov. 29 and 30, 2012, at Harvard University, in Cambridge, MA.  Each of you is cordially invited to join us in Cambridge for this, the latest in a series of NNIN process workshops that have been held at various NNIN sites over the last several years.

We are currently planning a 2-day program at Harvard CNS which will consist of the following:

Day 1. A 1-day staff "current status" review of NNIN ALD systems and capabilities at the various NNIN sites, with plenty of time for informal "shop talk".

Day 2.  A series of brief ALD vendor presentations, and a ~2 hour ALD User Seminar, where we plan to present a short review of the "day one" results, with a re-presentation one or two highlights of current staff work at NNIN sites, and then a Q&A session.   We will also be featuring 3 invited talks by noted experts in the field of ALD, to give us a broader perspective on our ALD work.

There will be no cost for this program, and it will be fully catered (breakfast and lunch).  Day One will be open to NNIN staff only, and Day Two will be open to (and advertised to) interested users and faculty, as well as others in the NNIN network.

The dates of this program are Thursday and Friday, Nov. 29-30, 2012 (concurrent with MRS Fall Meeting in Boston).  Registration is now open.  You can visit our "Event Page" here: 

http://www.cnf.cornell.edu/cnf_2012nninald.html


In the next few days, after primary NNIN ALD staff have a chance to sign up and arrange lodging, a general announcement and invitation will be sent out to a larger subset of NNIN staff.

Our hope is that each attending NNIN site will present a short overview of their site's current ALD status, including just a few slides with some salient details about their systems and process capabilities.  We will then compile a spreadsheet "database" of NNIN ALD capability, to act as a guide to users who come to any NNIN site with specific needs.  This will also serve as a template for similar entries in a broad "NNIN process capability" database, ultimately covering other processes such as dry etching, CVD and PVD deposition, etc.

The proposed "bullet point" list of info to be included can be found below.  It is likely that not everyone will have all of the desired information on all of their available films, but whatever is available will suffice.  This list may perhaps also serve as a template for future characterization work, as has been requested by NNIN leadership.

Here's the approximate list of desired info:  (Note:  We'd like to collect all of this data, but you won't necessarily need to present all of it in your presentation.  I'm working on a spreadsheet that we can each fill out that will compile as much of this as possible.)

**************

Films you have available
New films you are working on currently
Films you plan to explore or make available
Major issues you face  (equipment, process, users, scheduling, etc.)
Equipment usage level (% utilization, based on 24/7 or standard availability, if not 24/7)
Aspects you are studying for process enhancement
Your maintenance program/schedule
Equipment issues you have run into (pareto chart?)
Special modifications you have made

Process results (perhaps all on one table?) and Characterization Data
-      Rate/cycle  (incl. error bars)
-     Ref. Index
-  XPS, RBS, PL and/or Atom Probe data (and anything else of interest)

Electrical results (for dielectrics) and variables which may effect those results
-     Dielectric Constant
-     Breakdown Voltage (normalized)
-     Leakage (normalized)
-     Resistivity (for conductive films)
-     Variables

  o       O-ring material
o       Frequency of clean
o       Conditioning runs
o       N2 flow rate, Use of Ar instead of N2
o       High or low RF power
o       Cross-contamination
o       Precursor choice and purity level

 

SEM results (high aspect ratio images)
Results of graphene/CNT functionalization/nucleation efforts
Other Interesting Stuff
            Selective deposition, Al-doped ZnO

***************

As each group sends their compiled info, we will put it all in one big spreadsheet (or several), with data of user interest all together (i.e. films and systems available, typical film characteristics, etc.)  For the purposes of the presentations, we'd want to discuss your most interesting results, whether that's electrical data vs. temperature or contamination levels in HfO2, or your experiences with different precursors for the same film (which was better/worse, and why), and/or your most interesting or puzzling problems.  Also, we'd want to review a couple or three slides with your "compiled results", probably with some discussion of any results that stand out.  The idea is to see things you are doing that are working well, so we can imitate it, and to troubleshoot any areas where you might be having difficulty.

While it may look like a rather daunting list, I think you will agree it is all relevent and potential helpful to the other sites, and to our user base.  Not every group will have something to say on every topic, of course.  I will be generating my list as soon as possible, which I will then send around as at least one point of reference.

Hotels and B&Bs -

There is the usual complement of hotels within walking distance (not more than 1/2 hour), including the Sheraton Commander, The Inn at Harvard , The Charles Hotel, etc.  Varying levels of Fancy, cost probably a lot, but maybe some deals available.

Also, there several B&Bs within a few hundred yards of the symposium rooms, and I have confirmed that at least two of them have at least 10 rooms each for Wednesday and Thursday night.  These are The Irving House (irvinghouse.com), The Harding House (harding-house.com, 125-165/night).  There are three rooms available at A Bed and Breakfast in Cambridge (cambridgebnb.com, $155, shared bath).  Note that some rooms will have common (not private) bathrooms.

Food -   We're planning to have breakfast and lunch available both days, and dinner all together on Thursday evening.

Please pardon the "out-of-the-blue" aspect of this email.  We have been working on the preliminary aspects of this for a few weeks, so you have the "benefit" of getting all of the relevant information in one (rather big) batch.

If you are interested in attending, please sign up at your earliest convenience.  If you are not the primary ALD contact for your NNIN location, but you know who is, or know of others who would be interested in attending either day of the Symposium, please forward this as appropriate.

Please contact Mac Hathaway (hathaway@cns.fas.harvard.edu) with any questions. 

On behalf of the organizing committee (Mac Hathaway and Philippe de Rouffignac - Harvard CNS, Vince Genova - Cornell CNF, and Michelle Rincon - Stanford SNF), I thank you for attention.


Sincerely,

Mac Hathaway
Senior Process Engineer
Harvard Center for Nanoscale Systems
617-495-9012 (office)
617-259-0859 (cell)

Laminar hood problem in SNF Litho

Dear labmembers --

We've just been informed that two air transfer fans have failed so that
there is no laminar flow in part of the Litho area. Facilities is
working on a temporary repair which they expect will be done around 2 pm
today. The laminar flow hoods affected are the ones that serve L101
aisle (Karlsuss1/2, lithosolv, ASML) and L100 (ovens, YES, headway2.)

The litho area will remain open. However, we advise that if you have
any defect sensitive processes, you may want to delay work until the
laminar flow is back on later today.

Please also note that when the laminar flow comes back on later today,
it will be at 100% capacity rather than scaled back to 2/3 as it runs in
the rest of the lab and the L102 aisle (SVGcoat, SVGdev, EValign
systems). This will no doubt be louder and may result in odd air flow
patterns in the litho area. Facilities has ordered parts for repair,
but do not yet have an estimate as to when the parts are due in and
repairs can take place. We will update you as soon as we hear.

Thanks for your attention --

Your SNF Staff



--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
Paul G. Allen Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu

SU-8 2010 and AP-300 adhesion promoter

Hi,

I was wondering if anyone has SU-8 2010 and AP-300 in their personal stock. I just wanted to try out 1-2 wafers to see if it works for me. Also any advise in improving adhesion (besides HMDS) of SU-8 on glass is appreciated.

-Jyotindra

Looking for a wafer carrier in wbgen

Dear Labmember,
I am looking for the wafer carrier in wbgen. It is a big, brown one with a long handle, which could protect the frontside of the wafer for the KOH etch. It is not in Uli's wbgen bin as usual. If you happened to know where is it, please let me know.
Thanks,
Helen

Helen Qiushi Ran
=========================================
Department of Electrical Engineering
Stanford University, Stanford, CA 94305.
Mobile: +1-650-796-1439
Email: qran@stanford.edu

Etching Low stress silicon nitride

Dear Labmembers,

Which etching system and recipe gives the highest selectivity between
low stress silicon nitride and resist?

Thank you,
Liam

--
Dr. Liam O'Faolain
Ginzton Laboratory, Nano Building
348 Via Pueblo Mall, Stanford CA 94305, USA.

Re: Problem p5000etch SNF 2012-10-22 15:29:53: Chamber pressure fault

Calibrated chamber B throttle valve. Ran 4 wafers running the Jim-Ox recipe with no problems.

October fab cleaning scheduled for this Thursday night - Friday morning.

All,

The SNF facility will be unavailable beginning around 11:45pm Thursday and will re-open between 6:00-7:00am Friday morning.

If you have an urgent need for access to get samples or unload extended run experiments, contact me at 650-724-0847 for access.

Brett E. Huff

SNF Clean Room Manager

Stanford University

©510-612-8670

bhuff@stanford.edu

Reminder: Oral Exam Announcement: Tomas Sarmiento (Tuesday Oct. 23, 2PM, Allen-X Auditorium)

GaAs-based 1550 nm GaInNAsSb lasers


Tomas Sarmiento
Department of Electrical Engineering
Stanford University

Advisor: James S. Harris


Tuesday, October 23, 2012
2:00 PM (Refreshments served at 1:45 PM)
Allen-X Auditorium (formerly CIS-X Auditorium)

Low-cost, long-wavelength light sources are indispensable for the widespread deployment of fiber-to-the-home networks. Vertical cavity surface emitting lasers (VCSELs) are ideal for these applications due to their high fiber-coupling efficiency, low power consumption, simple packaging and wafer-scale manufacturability. In particular, VCSELs emitting in the C-band (1530-1565 nm) are highly desirable given that the fiber optical loss is minimal in this wavelength range. High-performance 1550 nm InP-based VCSELs using various distributed Bragg reflector (DBR) technologies have been demonstrated, but these approaches generally require complex and extensive processing. In contrast, GaAs-based VCSELs can be processed in a simple and robust way by exploiting the superior material properties of Al(Ga)As/GaAs DBRs and the oxidation of AlAs layers for electrical and optical confinement.

Dilute nitride GaInNAsSb alloys emitting in the 1200-1600 nm wavelength range can be grown coherently on GaAs substrates. Despite significant challenges in the growth of such highly-mismatched alloys, our group has demonstrated GaInNAsSb lasers with relatively low threshold current densities. In this talk, I will describe recent progress on the development of GaInNAsSb lasers. Optimization of the growth and annealing conditions enabled a four-fold enhancement of the photoluminescence efficiency of GaInNAsSb quantum wells. In addition, incorporation of GaAsP barriers significantly improved the temperature stability of the lasers. These growth advances enabled the realization of the first electrically-pumped GaInNAsSb VCSELs emitting in the C-band that operate at and above room temperature.




--
EE students mailing list
ee-students@lists.stanford.edu
https://mailman.stanford.edu/mailman/listinfo/ee-students

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Seminar: Materials – Back to the future

Materials – Back to the future

Time : Wednesday (10/24/2012) 4:15pm
Location : CIS-X 101
Speaker : Dipu Pramanik


Abstract

Recent Technology nodes are depending less on scaling feature size and replaced by the increasing use of novel materials and device architectures. The challenges of introducing new materials requires faster investigations of thin film stacks using Combinatorial techniques and platforms, such as those developed by Intermolecular. By coupling this with an improved understanding of bulk structures, defects and interfaces, device properties have continued to be improved from generation to generation. In this lecture we illustrate how new materials are being used in a variety of devices ranging from logic transistors to memory cells.

Speaker Bio

Dipu Pramanik is currently VP of Core Technology at Intermolecular Inc, responsible for developing the materials and device knowledge infrastructure. He has over 25 years experience in the semiconductor industry with focus on developing and deploying technology into high volume manufacturing. Prior to IMI, he was VP of the DFM business at Cadence Design Systems and at Synopsys, where he built up the TCAD division into a large business unit. He led the development of several generations of technology at VLSI Technology Inc, including process, packaging, reliability and design. He has been awarded more than 45 patents and has more than 100 publications in the area of materials, devices and design. He has a PhD in Physics/Materials Science from Cornell University and has taught at UC Berkeley and Oxford University.

Problem p5000etch SNF 2012-10-22 15:29:53: Chamber pressure fault

Unused SU-8 2050+

Dear SNF labmembers,

Does anyone have unused SU-8 2050, 2075 or 2100 that they would be willing to share? We do not plan to use more than 50 mL, and we can compensate the cost of any SU-8 used. Thanks in advance.

Best,

Kristen

-----------------

Kristen Lurie

Stanford Biomedical Optics Group

klurie@stanford.edu

650-725-6354

Comment p5000etch SNF 2012-10-21 08:05:05: Update

Completed weekly leak rate check on all three
chambers..

Campus Clean Up Event is Thursday, October 25th from 10:00A to 2:00P for SNF/Allen/AllenX building.

Dear All,

 

I hope everyone is aware that the FALL CAMPUS CLEAN-UP EVENT is going on (right now) throughout Campus.  It started October 2^nd and will go through November 8^th.   It runs each day, Monday through Friday from 10:00AM to 2:00PM.  The way it works is, the campus is broken up into Zones and SNF/Allen/AllenX building is located in Zone A and it’s slated to have its Clean Up Day, Thursday, October 25^th from 10:00A to 2:00P.  This is a GREAT opportunity to clean up your work space and maybe your department if you want to go the extra step(s) for yourself and your co-workers! 

 

The building’s drop off spot is the loading dock over at VARIAN not SNF.   

 

This event is being sponsored by Buildings and Grounds Maintenance (BGM) in conjunction with Peninsula Sanitary Service Inc. (PSSI).  If you need assistance in moving items to the Varian Loading Dock please let me know as soon as you can so, we can request help to move the item(s) if needed through Event Services.

 

The items that we can help you dispose of properly are:

 

Reusable Items:  Surplus Sales will be on site at the Varian Loading Dock to collect reusable items and electronics.

 

Electronics:  Surplus Sales will be on site to receive electronic equipment.  Electronic equipment cannot be placed in the dumpsters. 

 

Non-reusable Items:  PSSI will separate items for recycle.

 

Cardboard:  Please flatten corrugated cardboard before placing it in the green dumpsters.

 

Paper:  Place in specially marked paper recycling bins located at the Varian Loading Dock.  Please no binders, overhead sheets or plastic wrappers.

 

If you need ANY help getting your items over to the Varian Loading Dock, please email, call or come by my cubicle #41 on the first floor of the Paul G. Allen Building. We can discuss what you need to move how I can assist you.

 

Thank you,

 

Maureen

 

 

 

Ni etching?

Hi labmembers,

I have some wafers with 40nm Ni on top of 500nm Al. I'd like to etch the 40nm Ni layer while preserving the 500nm Al. I'm open to either wet or dry etching. Does anyone have any experience etching Ni? I'd like the selectivity between Ni and Al to be as high as possible, but it doesn't need to be super high. Any suggestions/experience would be appreciated.

Thanks for your help!

Azadeh

--
Azadeh Moini
Stanford University
Department of Electrical Engineering
amoini@stanford.edu

Re: Problem p5000etch SNF 2012-10-17 23:48:55: Chamber C operation stopped

clogged exhuast line cleaned

Re: Question: Etch rate of Unannealed 400degC LTO with 6:1 BOE wet etch

you will find this webpage a useful reference:

http://snf.stanford.edu/Process/WetProcessing/WetER1.html

On Thu, Oct 18, 2012 at 4:30 PM, Kyunglok Kim <kyunglok@stanford.edu> wrote:

Dear labmembers,

I'd like to use 6:1 BOE to etch a 1um thick LTO deposited at 400degC.
If 6:1 BOE etch rate is too aggressive, I also have a plan to use 50:1 HF instead of it.
Would you please let me know the average etch rate of both of them?
I really appreciate your help!

Best,
Kyunglok Kim
PhD Candidate
Electrical Engineering
Stanford University

Question: Etch rate of Unannealed 400degC LTO with 6:1 BOE wet etch

Dear labmembers,

I'd like to use 6:1 BOE to etch a 1um thick LTO deposited at 400degC.
If 6:1 BOE etch rate is too aggressive, I also have a plan to use 50:1 HF instead of it.
Would you please let me know the average etch rate of both of them?
I really appreciate your help!

Best,
Kyunglok Kim
PhD Candidate
Electrical Engineering
Stanford University

Re: missing multi-mask case with 2 masks inside

The mask case is actually transparent, but with masks inside it would appear brownish.

I would really appreciate it if someone knows where it is.

Thank you.

Mike

On Thu, Oct 18, 2012 at 3:53 PM, Mike Tan <mt.innovate@gmail.com> wrote:

Hi

Has anyone seen any transparent brown mask case with 2 masks inside?  It's a case that has the capacity for about 10 masks.  I think I left it in the cleanroom Wednesday of last week.

If anyone finds it, please let me know.

Thank you very much for your help.


Mike Tan (mtan)

missing multi-mask case with 2 masks inside

Hi

Has anyone seen any transparent brown mask case with 2 masks inside?  It's a case that has the capacity for about 10 masks.  I think I left it in the cleanroom Wednesday of last week.

If anyone finds it, please let me know.

Thank you very much for your help.


Mike Tan (mtan)

SOI wafers needed (thin Si, thick SiO2)

Hello labmembers!

Do you have extra SOI wafers that I could buy/borrow from you? I'm looking for wafers with top silicon thickness 200-400nm and buried oxide thickness 1um or thicker.

Thanks in advance,

Emel

Problem p5000etch SNF 2012-10-17 23:48:55: Chamber C operation stopped

The etching recipe stopped when there was 6 seconds left in the pumping step. Then I tried the recipe again and it stopped before the recipe started.

Purchasing offcut sapphire wafers

Hi labmembers,

What are some good vendors from where can I purchase offcut sapphire wafers?

Specifically, I'm looking for 2-inch one side polished c-plane wafers that are offcut about 0.3-0.4 degrees in either the a-plane or m-plane directions.

Any leads would be appreciated!

Thanks,

Vijay Parameshwaran
vijayp@stanford.edu

NAND Flash Memory: Basics, Key Scaling Challenges and Future Outlook

NAND Flash Memory: Basics, Key Scaling Challenges and Future Outlook


Time : 4:15pm (10/17/2012)
Location : CIS-X 101
Speaker : Pranav Kalavade


Abstract

This talk will start with device basics of FG memory devices, and cover some basic operation of the NAND flash cell. This will be followed by highlighting the scaling challenges, giving examples of solutions that industry has developed along the way. The talk will conclude with some comments about future directions that are being explored in the industry.

Bio
Pranav is a Principle Engineer in the Non-volatile Solutions Group at Intel. His early work was on NOR flash cell on the 90nm node. Later, he was part of the initial technical team leading the Intel-Micron NAND JDP, and has worked on NAND for multiple nodes starting with the 50nm technology, and currently working on 20nm technology. Pranav has served as a panelist of several conferences. He previously served as the Financial and Technical and is currently General Chairman of the IEEE International Memory Workshop. Pranav received his B. Tech (EE) from IIT Bombay, India, M.S. (EE) from Purdue University, and a Ph.D. from Stanford University. Pranav has several publications in technical journals and conferences, and holds 7 patents with several applications that are currently pending.

Comment p5000etch SNF 2012-10-16 18:35:31: Chamber A

Vented chamber and changed large lip seal. Checked and
verified backside He leak at 1.3sccm, also wet cleaned chamber.

Sonny Vo's Defense Friday 2pm CisAud. Reception at 1:45pm

Dear labmembers,

After 5+ years of working alongside so many of you, i am ready to depart our stone roof museum. I leave with so many fond memories working day and nights with so many of you. The staffs, from Mary and Ed who had helped me get started with my 8 masks process flow during my first two years to Maurice who only just a few months ago held my hand through a critical wafer dicing operation. I feel truly lucky to be around such outstanding people that i do not want to work anywhere else but nearby.

 So what i ended up doing was I went down the street along PageMills, knocked on the door of HP Labs and convinced them to give me a job in exchange for some boy scout cookies i had bought in front of the San Antonio Walmart. It worked! 21st century entrepreneurship at work here.  Some of you are probably saying 'oh crap!' but yes you haven't gotten rid of me yet! :) 

Warmest Regards,
Sonny

----
Department of Applied physics, Stanford University
research group: http://snow.stanford.edu/index.html
626-216-4597

Towards Near Field Applications using Nano-Aperture VCSELs: 

Near-field optical microscopy requires extremely high optical fields in proximity to the object being probed.  However, when light propagates through conventional circular or square shaped apertures, the power-throughput decays as the fourth power of the aperture size. We present a vast diversity of unconventionally-shaped apertures exhibiting extra-ordinary enhancement in both power transmission and near-field intensity that can be one million times greater than the conventional circular- or square-shaped apertures. These apertures can be shaped like a C , an L or a bowtie.   They can also be iterated into a fractal-structure resulting in many interesting optical properties or can be enhanced by plasmonic rings. Experiments using electron-energy loss spectroscopy (EELS) with sub-nanometer resolution revealed the near-field spot-size and the plasmon energy ranges of the apertures.

 

These unconventional apertures and arrays of such apertures were incorporated into Vertical cavity surface emitting lasers (VCSELs); this integrated near-field device demonstrated a power density of 50mW/μm², five times larger than the power density required for high-density optical recording. Finally, a novel architecture that combines a VCSEL with an NSOM-like tip (VCSEL nanoscope) into an integrated device will be presented.  The VCSEL nanoscope can serve as a powerful device to manipulate and probe the nanoscale such as single molecule manipulation and detection, high throughput wafer defect detection and near-field coupling to waveguides for optical interconnects.