Title: Novel Capacitorless Single-Transistor DRAM Technologies
Research Advisor: Prof. Krishna Saraswat
Date: Friday, May 14, 2010
Time: 10:00 am
Location: CIS-X Auditorium (Allen Building)
Abstract:
The Dynamic random access memory (DRAM) industry has achieved miracles packing more and more memory bits onto ever smaller silicon die. But, the scaling of the conventional 1Transistor/1Capacitor (1T/1C) DRAM is becoming increasingly difficult, in particular due to the capacitor which has become harder to scale, as device geometries shrink.
Recently the capacitorless single-transistor (1T) DRAMs have attracted attention, due to its ability to achieve higher memory cell density and to solve the problems associated with the scaling of the capacitor. The information is stored as different charge levels at a capacitor in conventional 1T/1C DRAM, whereas the 1T DRAM employs floating body effects within the transistor to store the information without the need of the capacitor.
The absence of the capacitor is advantageous in terms of scalability, process and fabrication complexity, and compatibility with the logic processing steps, device density, yield and cost. Due to all these advantages of the capacitorless DRAM, and to solve the scaling problem of conventional 1T/1C DRAM, this work is focused on creating novel single transistor DRAM technologies.
The first device that is studied is vertical double-gate (DG) capacitorless single-transistor DRAM (1T VR DRAM). This device has advantages of being vertical with a small footprint, it can be integrated on bulk Si and being a double-gate device allows better electrostatic control of the channel and higher intrinsic device retention.
The second device that is investigated is a novel DRAM device: capacitorless single-transistor quantum well DRAM (1T QW DRAM), which employs energy-band engineering approach within the body of the transistor in order to create a "hole storage pocket" and "carrier distribution control layer" which results in superior device characteristics in terms of scalability and memory sensing window.
The third and the final device that is studied is also a novel DRAM device: capacitorless single-transistor charge trap DRAM (1T CT DRAM). The body of this device is engineered with the intentional charge traps so as to obtain a memory effect. This novel DRAM relies on the existence and absence of electrons within its body and uses a charge-trapping mechanism in its memory operation, unlike conventional 1T DRAMs that rely on holes and employ floating-body effects in its memory operation.
