Breast Cancer 3-Day Walk (fwd)

Dear Friends,

This year, I'll be participating in a very special event called the Breast
Cancer 3-Day.

I'll walk 60 miles over the course of three days with thousands of other
women and men. The net proceeds will support breast cancer research,
education, screening and treatment through Susan G. Komen for the Cure and
the National Philanthropic Trust Breast Cancer Fund.

Every advancement in breast cancer research, treatment, education and
prevention in the last 25 years has been touched by a Komen for the Cure
grant.
They are working hard to build a future without breast cancer, and I plan on
raising $2,300 to help bring us closer to that goal. I know I can raise even
more than that with your help and support.

You can donate online at http://www.the3day.org/. Just click on Donate Now
and search for my personal fundraising page. Or fill out the enclosed
donation form and mail it to the address on the form. You can also call
800.996.3DAY to donate over the phone.

This cause means alot to me as I have lost good friends to cancer and seen
survivors suffer with this terrible disease.

According to Susan G. Komen for the Cure, more than 200,000 American women
will be diagnosed with breast cancer this year, and nearly 40,000 will die
from the disease. That's why I'm walking so far, to do something bold about
breast cancer. I hope that you'll share this incredible adventure with me by
supporting me in my fundraising efforts.

Because everyone deserves a lifetime.

Thank you for taking the time to read this letter, and thank you in advance
for your generosity!

Sincerely,
Jasmine Hasi

P.S. Don't wait - donate today!

Please visit The Breast Cancer 3-Day today!

<a
href="http://www.the3day.org/site/TR/Walk/SanFranciscoBayAreaEvent?px=170014
5&pg=personal&fr_id=1299&et=-iqJYG6O4RoL-M4zs55ZAA..&s_tafId=84981">Click
here to visit
my personal page.</a><br />

<span class="Smaller">If the text above does not appear as a clickable link,
you can visit the web address:<br />
http://www.the3day.org/site/TR/Walk/SanFranciscoBayAreaEvent?px=1700145&pg=p
ersonal&fr_id=1299&et=-iqJYG6O4RoL-M4zs55ZAA..&s_tafId=84981</span>
</p>

<p>
<a
href="http://www.the3day.org/site/TR/Walk/SanFranciscoBayAreaEvent?team_id=5
6820&pg=team&fr_id=1299&et=kL7s8p_-bAJ1ryTW1Iz2mQ..&s_tafId=84981">Click
here to view
the team page for Boob Brigade</a><br />
<span class="Smaller">If the text above does not appear as a clickable link,

you can visit the web address:<br />
http://www.the3day.org/site/TR/Walk/SanFranciscoBayAreaEvent?team_id=56820&p
g=team&fr_id=1299&et=kL7s8p_-bAJ1ryTW1Iz2mQ..&s_tafId=84981</span>
</p>

<img
src="http://www.the3day.org/site/PixelServer?tr=puHpEhiF6upE6yMIkUmHMw.."
height="1" width="1">

For more information about the Breast Cancer 3-Day, Susan G. Komen for the
Cure
or the National Philanthropic Trust Breast Cancer Fund, visit
http://www.the3day.org/ or call 800.996.3DAY.

CMP papers?

Dear Labmembers,

Has anyone heard of, or published, papers with examples of novel CMP
usage in the last few years? Someone I know is writing a journal
review and would like input from the SNF community.

Thanks!

Liz
ehe@stanford.edu

Resist swap

I have an unopened 500mL bottle of SU8-2010 that I am willing to trade for some SU8-2050. Anyone interested please contact me (maloney1) at the following e-mail address: maloney1@stanford.edu

Mike

Michael T. Maloney
Postdoctoral Scholar
Department of Neurology and Neurological Sciences
Stanford University School of Medicine
P222 MSLS
ph: (650) 498-8112

ASML Customer Workshop at SNF - Tuesday, March 31, 2009 - 12 noon to 5 pm

Reminder - today.

-----------------------------------------------------------------------------------------------------------------------------------------

On behalf of ASML and Keith Best, you are invited to their Customized Imaging Solutions customer workshop on Tuesday, March 31, 2009 from 12 noon to 5 pm.  In order to get a proper count for the lunch ASML is providing, please register at:

http://www.surveymonkey.com/s.aspx?sm=fJEcP3GkvBdm3b_2bFqy5Mjg_3d_3d

---

From: ASML CIS [ mailto:michael.pullen@asml.com]
Sent: Wednesday, March 04, 2009 12:37 PM
To: Keith Best
Subject: ASML CIS Customer Workshop at Stanford Nanofabrication Facility (SNF)

 
ASML CIS Customer Workshop at Stanford Nanofabrication Facility (SNF)

    
Please Register to Attend
Agenda
12:00 PM Lunch

1:00 PM Welcome & Introduction - Keith Best (ASML)
1:10 PM MEMS Market and ASML Solutions - Keith Best (ASML)
1:40 PM Recent results from Stanford/ASML - JDA Paul Rissman (SNF)
2:10 PM Canadian Photonics Fabrication Center's approach to patterning - Simon Wingar (CPFC)
2:30 PM GE - ASML small piece handling project - Keith Best (ASML)
2:50 PM Quick-turn device development w/ASML's compound image design software (CID)- Paul Schuele (Sharp)

3:10 PM Coffee Break

3:30 PM ASML CIS demo update - Vinny Pici (ASML)
4:00 PM TFH market and ASML solutions - Keith Best (ASML)
4:30 PM Leveraging Lithography Toolsets in a Development Foundry-SVTC - Mary Zawadzki(SVTC)

5:00 PM Close

Please respond by filling out the registration form.
Go to Registration Form


Date: Tuesday, March 31st
Time: 12:00 PM - 5:00 PM
Location: SNF Auditorium, Paul Allen Center for Integrated Systems (CIS) Extension
Visitor Information

© Copyright 2009 (ASML) All rights reserved | ASML Netherlands B.V., De Run 6501, 5503 LA Veldhoven, The Netherlands
  Legal Terms and Conditions | Privacy Policy

-- The information contained in this communication and any attachments is confidential and may be privileged, and is for the sole use of the intended recipient(s). Any unauthorized review, use, disclosure or distribution is prohibited. Unless explicitly stated otherwise in the body of this communication or the attachment thereto (if any), the information is provided on an AS-IS basis without any express or implied warranties or liabilities. To the extent you are relying on this information, you are doing so at your own risk. If you are not the intended recipient, please notify the sender immediately by replying to this message and destroy all copies of this message and any attachments. ASML is neither liable for the proper and complete transmission of the information contained in this communication, nor for any delay in its receipt.

wafer sawing

Dear Lab members

Please let me know of a company, which can

1. Cut a 12 inch wafer into a few 4 inch wafers.

2. Cut a 12 inch wafer into 2 cm X 2cm square pieces.

3. Cut a 4 inch wafer into 2 cm X 2cm square pieces.

please let me know

thanks
~gaurav

SiC films

Is there a CVD system at SNF for SiC film deposition? Any information on how to deposit SiC and Si rich SiC films would be welcome

 

Thanks

WM.
-------------------------------------------------------
PhD Candidate,
Salleo Research Group,
Electrical Engineering,
Stanford, CA

Microscope Update 3/27/09

Hi Labmembers...

Just a quick microscope update:

1. The microscope in diffusion that was sent out for repair is back and re-installed/tested. The only thing thjat does not work is the video camera. It appears that the computer hard disk is corrupted or crashed. We either get the blue screen or "invalid harddisk error. Still need to investigate and repair. Microscope OK to use.

2. The microscope in litho, across from the granite has been removed and sent out for repair. We have installed a temporary microscope in its place. The video camera is also installed on the microscope and is functional.

..Gary

CD-26 resist developer. Fw: Does any one have TMAOH (tetramethylammonium hydroxide)?

It's also called CD-26 resist developer.

Thank you!

Ying

 

----- Original Message -----

From: Ying Chen

To: labmembers@snf.stanford.edu

Sent: Wednesday, March 25, 2009 9:30 PM

Subject: Does any one have TMAOH (tetramethylammonium hydroxide)?

Can I borrow a little or can you give me some ordering information?

 

Thanks!

Ying

Does any one have TMAOH (tetramethylammonium hydroxide)?

Can I borrow a little or can you give me some ordering information?

 

Thanks!

Ying

Labmembers' Meeting, Friday, March 27, 1 pm

Greetings Labmembers --

There will be a Labmembers' Meeting this Friday, March 27, at 1 pm in
the CISX Auditorium. On the agenda: Lab and Quality Circle Updates,
including a discussion of the innotec. Be there or be... unaware...

Your SNF Staff

--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu

Comment p5000etch SNF 2009-03-25 13:12:39: Update root directory full

Field service did not find any problem with the system. He suggested re-formatting the hard drive and re-istalling the software. Will need to coordinate with users and also need to verify that everything is backed up before we reformat the drive.

1/2 OFF Bake Sale in the Breakroom at 9:30A

Dear All,

 

We had a lot of contributors to our bake sale yesterday and we have some great inventory left.  Please come down to the breakroom at 9:30 this morning and get some bake goods for ½ off while they  last.

 

Thank you for your wonderful support,

 

Maureen

 

Maureen Baran

Stanford Nanofabrication Facility

Lab Services Administrator

mbaran@stanford.edu

650-725-3664

 

ASML Customer Workshop at SNF - Tuesday, March 31, 2009 - 12 noon to 5 pm

Reminder - register by Friday if you would like to attend this workshop.

-----------------------------------------------------------------------------------------------------------------------------------------

On behalf of ASML and Keith Best, you are invited to their Customized Imaging Solutions customer workshop on Tuesday, March 31, 2009 from 12 noon to 5 pm.  In order to get a proper count for the lunch ASML is providing, please register at:

http://www.surveymonkey.com/s.aspx?sm=fJEcP3GkvBdm3b_2bFqy5Mjg_3d_3d

---

From: ASML CIS [ mailto:michael.pullen@asml.com]
Sent: Wednesday, March 04, 2009 12:37 PM
To: Keith Best
Subject: ASML CIS Customer Workshop at Stanford Nanofabrication Facility (SNF)

 
ASML CIS Customer Workshop at Stanford Nanofabrication Facility (SNF)

    
Please Register to Attend
Agenda
12:00 PM Lunch

1:00 PM Welcome & Introduction - Keith Best (ASML)
1:10 PM MEMS Market and ASML Solutions - Keith Best (ASML)
1:40 PM Recent results from Stanford/ASML - JDA Paul Rissman (SNF)
2:10 PM Canadian Photonics Fabrication Center's approach to patterning - Simon Wingar (CPFC)
2:30 PM GE - ASML small piece handling project - Keith Best (ASML)
2:50 PM Quick-turn device development w/ASML's compound image design software (CID)- Paul Schuele (Sharp)

3:10 PM Coffee Break

3:30 PM ASML CIS demo update - Vinny Pici (ASML)
4:00 PM TFH market and ASML solutions - Keith Best (ASML)
4:30 PM Leveraging Lithography Toolsets in a Development Foundry-SVTC - Mary Zawadzki(SVTC)

5:00 PM Close

Please respond by filling out the registration form.
Go to Registration Form


Date: Tuesday, March 31st
Time: 12:00 PM - 5:00 PM
Location: SNF Auditorium, Paul Allen Center for Integrated Systems (CIS) Extension
Visitor Information

© Copyright 2009 (ASML) All rights reserved | ASML Netherlands B.V., De Run 6501, 5503 LA Veldhoven, The Netherlands
  Legal Terms and Conditions | Privacy Policy

-- The information contained in this communication and any attachments is confidential and may be privileged, and is for the sole use of the intended recipient(s). Any unauthorized review, use, disclosure or distribution is prohibited. Unless explicitly stated otherwise in the body of this communication or the attachment thereto (if any), the information is provided on an AS-IS basis without any express or implied warranties or liabilities. To the extent you are relying on this information, you are doing so at your own risk. If you are not the intended recipient, please notify the sender immediately by replying to this message and destroy all copies of this message and any attachments. ASML is neither liable for the proper and complete transmission of the information contained in this communication, nor for any delay in its receipt.

Process Clinic, Monday, 3/23, 2-4 pm

Hi all --

The next Process Clinic will take place this Monday, March 23,
from 2-4 pm, in the cubicle area near Maureen's office. Bring
your process flows, your layouts, your wackiest ideas. It'll be fun.

Your SNF Staff

--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu

Deadline TODAY 11:59pm: Retreat Sign Ups for SUPR 2009

There are only a very few spots left for this amazing retreat in Monterey in *the best* hotel in the area. Posters can easily be from your most recent conference, so don't delay in registering today! (http://supr.stanford.edu/registration/) (Poster submission Titles and authors not required until March 27).

Currently, we have people from very diverse fields making this a truly unique opportunity to collaborate with students in departments such as Chemistry, Biology, Material Science, Physics, Applied Physics and EE. Sign up now to reserve your spot before they are all filled!

If you cannot view the above announcement, you may access it at http://supr.stanford.edu/SUPR_2009_Flyer

--
--------------------------------------------------
Meredith M. Lee
Stanford University
Ph.D. Candidate, Dept. of Electrical Engineering
President, Stanford Student OSA/SPIE

Center for Integrated Systems
420 Via Ortega, Stanford, CA 94305-4075
Fax: (650) 723-4659
mmlee@stanford.edu

--
Sara Charbonneau-Lefort
------------------------------------
Assistant Director
Stanford Photonics Research Center
ph: 650-723-5627
fax: 650-725-1822
http://photonics.stanford.edu
---------------------------------------------------------

HF etch rate of PECVD SiN

Dear all, I was wondering if anybody studied concentrated HF etch rate of PECVD SiN films at SNF or elsewhere. Specifically I would like to know what range of minimum etch rate we can expect with a recipe limited to ~400 C temp range. Etch rates in BOE will give some hint as well. Also, any information on correlation between etch rate and process parameters (freequency, prsessure, gas ratios etc,) or other measurable physical parameters (e.g refractive index, stress) would be very useful. Best regards, Erhan Ata General MEMS Corp.

Fwd: IMAPS Northern California Chapter, Lunch Presentation on April 1

FYI.

Begin forwarded message:

From: "Steve Greene" <sgreene@imaps.org>

Date: March 19, 2009 11:15:35 AM PDT

To: undisclosed-recipients:;

Subject: IMAPS Northern California Chapter, Lunch Presentation on April 1

 

 

IMAPS Northern California Chapter 

 Wednesday, April 1, 2009 at 11:30

Please join us for a technical presentation and lunch.

 

The speaker is Mr. Marc Robinson of Vertical Circuits, Inc.  His presentation on "Conductive Polymer Interconnects for Low Cost Chip Scale Packages" will review the characteristics of conductive polymers used for chip and package interconnections that can be built without wire bonds.  

Mr. Robinson is an industry veteran with significant experience not only of technology development, but also in business-IP aspects.

 

We would appreciate your forwarding this announcement to any of your colleagues and friends who you think might be interested.

 

 

This lunch meeting will be held at The Lookout, 605 Macara Avenue, Sunnyvale, CA 94086.  Please note that this is a new location.

Please respond to Gina Love at glove@cctlaser.com to make your lunch reservations by Friday, March 27.

We look forward to seeing you at this event. 


Best Regards,

Guna Selvaduray
San Jose State University
gunas@email.sjsu.edu
Phone: (408) 924-3874

 

To unsubscribe from these member e-mails, please reply with UNSUBSCRIBE in the subject line.

 

 

TMAH/KOH etch stop on SiO2

Hello,

 

            I have a question about using TMAH/KOH as a (poly)silicon blanket etch and its ability to stop on a thin doped oxide without attacking silicon below the doped oxide.

 

            Does TMAH/KOH etch n-doped oxide? If so are there ways around this? Insights would be appreciated. Is there a silicon etch which can stop on a thin n-doped SIO2?

 

            Thanks!

                        Arvind Kamath

Pt paste

Hi,

 

Is there anyone who has Pt paste (or Au paste) and is willing to give some to me? The total quantity that I need is small; I just need to paint over an area smaller than 1.5 cm^2.

 

Thanks,

Byungha 

Eun Ji Kim's Dissertation Defense Thursday 3/19 2pm Packard 202

Interface and Defect Study of High Permittivity Dielectrics on Si and III-V semiconductors

Eun Ji Kim

Advisors: Prof. Paul C. McIntyre

Prof. Krishna C. Saraswat 
 
Date: Thursday, Mar. 19, 2009
Time: 2:00 PM (Refreshments served at 1:45 PM)
Location: Packard Bldg. Rm. 202
 

 

        In an effort to decrease electronic device dimensions and improve device performance, high permittivity dielectrics have been introduced to metal-oxide-semiconductor field effect transistors (MOSFETs). Even though replacing SiO2 with high permittivity dielectrics enabled aggressive device scaling, however, the introduction of new materials gave rise to fundamental problems that could lead to device performance degradation, such as reduction of the effective carrier channel mobility and threshold voltage instabilities. Unsatisfied dangling bonds at the interface of the high permittivity dielectrics and Si, intrinsic and extrinsic point defects in high permittivity dielectrics, and remote phonon scattering are believed to cause degradation of device performance. To understand the limitations to the performance of MOSFETs with high permittivity dielectrics, it is critical to probe phonon modes and defect states directly in high-k dielectrics.
        Inelastic electron tunneling spectroscopy (IETS) is employed to study soft phonon modes and defect states in HfO2 grown by atomic layer deposition (ALD) on Si. Observed spectral features suggest that monoclinic- and tetragonal- HfO2 vibrational modes exist in the annealed HfO2 while crystalline HfO2 vibrational modes are not detected in the as-deposited samples, consistent with selective area electron diffraction analysis. In addition to soft phonon modes of HfO2, changes in amplitude and energy of spectral features were observed as the bias condition changes. We attribute these features to defect-related states in HfO2 and analyze them in terms of electron energy states in the HfO2 bandgap and reported oxygen vacancy states in HfO2.
        For further device scaling, III-V compound semiconductors are receiving increasing attention for channel replacement in the metal-oxide-semiconductor (MOS) technology beyond 22 nm node because of their high intrinsic electron mobility. Unlike SiO2 that exhibits excellent passivating properties on Si with low interface state densities, there typically exists a large density of defect states at the interface of III-V semiconductors and their native oxides. Previous research on GaAs showed that less than 1 % of a monolayer of chemisorbed O2 can pin the Fermi level at the semiconductor surface. Therefore, suppressing oxidation of the III-V semiconductors' surface prior to and during gate dielectric deposition could be essential to achieving device performance superior to that of silicon in nanoscale devices. Several different approaches have been demonstrated to prepare III-V semiconductor-based MOS devices. However, previously attempted methods resulted in frequency-dependent flat band voltage (Vfb) shift, charge trapping in the dielectrics and a relatively high density of interface trap states, possibly from unintentional oxidation of the III-V channel.
        We used In0.53Ga0.47As (100) channels that were capped with an arsenic layer after channel epitaxial growth to avoid III-V oxidation during exposure of the samples to air. The As capping layer was thermally desorbed in-situ in a load-locked ALD reactor prior to Al2O3 gate dielectric deposition. By preventing subcutaneous oxidation of the channel surface, we obtained unpinned Al2O3/In0.53Ga0.47As interfaces with a low density of interface states. The C-V characteristics show a hysteresis of less than 40 mV and relatively small frequency dispersion in accumulation. The surface potential swing (0.44~1.2 eV) calculated using the Berglund integral suggests the absence of a high density of midgap interface states. The observation of near-ideal flat band voltage values for Pt- and Al-electroded MOS capacitors indicates the absence of a significant interface dipole. The temperature-independence of the frequency dispersion of the accumulation capacitance and its scaling with measurement frequency are consistent with tunneling of carriers into defects in the Al2O3 layer, border traps. This also indicates a low interface state density for these devices.
 

Re: Shutdown p5000etch SNF 2009-03-16 14:59:52: wafer cannot be unloaded

Recovered wafer from load lock...

Missing jacket

Sorry for the spam, but I think someone accidentally grabbed my jacket from outside the gowning room today. If you get home and have a new blue sweatshirt with a zipper, shoot me an email. Thanks!

- joey

Shutdown p5000etch SNF 2009-03-16 14:59:52: wafer cannot be unloaded

I load a program for chamber C, but selected B only by mistake. The process aborted but the wafer isstuck in loadlock chamber.

Re: Spin-on dopants

I emailed Aaron separately, but in case anyone else is interested before I have a chance to post this to the wiki, here are spreading resistance analysis profiles for 800C/35min and 850C/15min in tylan6. You can obtain very highly doped n-type silicon and use thermal oxide (500A-1000A thick) in order to mask the diffusion to selectively dope regions of your wafer, then remove the POCl3 and oxide with a quick HF dip afterwards.

- joey

On Mon, Mar 16, 2009 at 11:30 AM, Chris Kenney <kenney@slac.stanford.edu> wrote:

Hi Aaron,

Can you use the gaseous doping tubes: tylan5 and tylan6? Your
wafers must be CMOS-clean to use these tubes.

Chris

On Mon, 16 Mar 2009, Aaron Hryciw wrote:

Hello,

Does anyone have experience with phosphorus-containing spin-on dopants?  I
want to make an ohmic contact to n-type Si (P-doped, ~10^15 cm^-3), so I

would like to bring up my doping levels to >10?19 cm^-3 under my contacts.

I would greatly appreciate any advice you can give me regarding suppliers
and/or recipes that have produced good results at SNF.

Cheers!

? Aaron


--
Dr. Aaron Hryciw
Postdoctoral Scholar
Geballe Laboratory for Advanced Materials
Stanford University
476 Lomita Mall (04-490)
McCullough Building, Rm. 325
Stanford, CA  94305-4045

Tel.:  (650) 723-5840
Fax.:  (650) 736-1984

Re: Spin-on dopants

Hi Aaron,

Can you use the gaseous doping tubes: tylan5 and tylan6? Your
wafers must be CMOS-clean to use these tubes.

Chris

On Mon, 16 Mar 2009, Aaron Hryciw wrote:

> Hello,
>
> Does anyone have experience with phosphorus-containing spin-on dopants? I
> want to make an ohmic contact to n-type Si (P-doped, ~10^15 cm^-3), so I
> would like to bring up my doping levels to >10?19 cm^-3 under my contacts.
> I would greatly appreciate any advice you can give me regarding suppliers
> and/or recipes that have produced good results at SNF.
>
> Cheers!
>
> ? Aaron
>
>
> --
> Dr. Aaron Hryciw
> Postdoctoral Scholar
> Geballe Laboratory for Advanced Materials
> Stanford University
> 476 Lomita Mall (04-490)
> McCullough Building, Rm. 325
> Stanford, CA 94305-4045
>
> Tel.: (650) 723-5840
> Fax.: (650) 736-1984
>

Spin-on dopants

Hello,

Does anyone have experience with phosphorus-containing spin-on dopants?  I want to make an ohmic contact to n-type Si (P-doped, ~10^15 cm^-3), so I would like to bring up my doping levels to >10ˆ19 cm^-3 under my contacts.  I would greatly appreciate any advice you can give me regarding suppliers and/or recipes that have produced good results at SNF.

Cheers!

 – Aaron


--
Dr. Aaron Hryciw
Postdoctoral Scholar
Geballe Laboratory for Advanced Materials
Stanford University
476 Lomita Mall (04-490)
McCullough Building, Rm. 325
Stanford, CA  94305-4045

Tel.:  (650) 723-5840
Fax.:  (650) 736-1984

Free Electro-mechanical Components

Hi All...

The SNF lab is in process of removing and discarding a vintage tool from the lab.The system is a Nikon body 4 wafer stepper. Before we dispose of it, we are offering up any components that may be of use to the engineering community. Here is a list if items that can be salvaged and reused:

1. DC Power supplies

2. Cooling fans

3. Interconnect cabling

4. Electronic components

5. Switches, potentiometers, meters. ect..

6. Miscellaneous hardware

These items will be available until Wednesday(3/18) after which we will dispose of them. If you are interested, we are moving the items to the CIS loading dock( Paul G Allen Building ) for your viewing. It is your responsibility to dis-assemble and remove any parts that you want, or make other arrangements as needed. However, Wednesday is the deadline and all will be gone. There may be more available at a later date as we are still de-installing and removing the main body of the tool. Items may include optically flat granite surface, interferometer system, miscellaneous optical components, electro-mechanical subsystems.

If you are interested, please stop be the CIS loading dock and have a look. The items will be marked "Free Stuff". If you have any questions, get a hold of Gary( 5-1685) or Mario( 5-5538) and we will happy to point out the items.

Thanks... Gary

Defense announcement on 3/16 monday

Title: Development of Piezoresistive Microcantilever based Force Feedback System for Study of Mechanotransduction in C. elegans

University Oral Examination
Sung-Jin Park
Department of Mechanical Engineering
Stanford University
Advisor: Beth Pruitt and Miriam Goodman

Date: Monday, March 16, 2009
Time: 10AM (Refreshments served at 9:45AM)
Location: Building 300- room 300 (Auditorium) (map attached)

Abstract:

 

Cellular mechanotransduction, the conversion of force into to an electrical or biochemical signal, is a fundamental process essential to normal life, including hearing, touch and balance. Among these, touch sensation is the least understood. The nematode Caenorhabditis elegans is one of the most powerful model organisms in which to analyze the mechanism of touch sensation. Few techniques exist to provide forces and displacements appropriate for such studies. To address this technological gap, we developed a metrology using piezoresistive cantilevers as force-displacement sensors coupled to feedback system in order to apply and maintain defined load profiles to micron-scale animals. This thesis presents 1) design and optimization of piezoresistive cantilever, 2) integration and development of force clamp system, and 3) biological studies of C. elegans mechanotransduction.

 

We developed and validated an analytical model to predict the force sensitivity and force resolution of a piezoresistive cantilever. We systematically analyzed the effects of process parameters on the sensitivity and resolution of the cantilevers to optimize their design. This optimization technique produced optimal cantilever with minimum resolution such as 69 pN at 1-1000 Hz bandwidth. This analytical model and optimization technique are very useful to design piezoresistive devices with complex design conditions for biological applications.

 

We conducted biological studies of C. elegans mechanotransduction by integrating the developed force probe with force and displacement feedback system. We measured body stiffness of wild type and mutants which alter body shape and cuticle proteins. The analysis of C. elegans body mechanics suggests that shell mechanics dominates stiffness rather than hydrostatic pressure. We also conducted the behavioral response of C. elegans to touch stimuli by utilizing the system in force-clamping mode. We applied a 100 nN to 10 mN force to freely-moving wild type and mec-4 mutant which has loss of touch receptor neuron. The behavioral result agrees with our prior in-vivo work which suggests that electrical responses of wild type to touch saturate near a force threshold, between 100nN and 1mN. These studies form a part of the bigger puzzle of how body mechanics affect locomotion and force sensing.

Cell Phone Found in the CIS Auditorium this Afternoon.

A cell phone was found in the CIS Auditorium this afternoon, if it is yours, please come and claim it.  The phone is dead so, we are unable to contact you.

 

I’m in cubicle #41 on the first floor of the CIS building.

 

Maureen

 

Maureen Baran

Stanford Nanofabrication Facility

Lab Services Administrator

mbaran@stanford.edu

650-725-3664

 

Stretchable Silicon for Photovoltaic Panels, etc (Friday, 12pm, McCullough 115)

Stanford Nanoscience & Nanotechnology Society Seminar:

Stretchable Silicon for solar panels, sensor networks, and flat-screen TVs. 

Kevin Huang (Prof. Peter Peumans group)

When: Friday March. 13th 12pm
Where: McCullough Rm 115 .
Free Food (pizza) served at 11:45am

For more information please visit http://nanosociety.stanford.edu

Reminder: Salman Latif PhD Orals Thursday, 2:30pm, CIS-X Auditorium

************************************************************************
University Ph.D. Oral Examination

Low Capacitance Silicon CMOS Photodetectors for Optical Interconnects

Salman Latif

Department of Electrical Engineering
Stanford University

CIS-X Auditorium (X-101)

Thursday, March 12, 2009
2:30 PM - 3:30 PM
(Refreshments served at 2:15 PM)

************************************************************************

The feasibility of Silicon as a platform for optoelectronics has
generated intense research efforts and publicity in the last few
years. One of the areas in which these advances in Silicon photonics
have the potential to make an impact is the interconnect part of
electrical systems. As data rates scale to higher speeds, electrical
interconnects require increased power dissipation and signal
processing complexity. For example, interconnects take up to 50% of
microprocessor power, and this portion is expected to rise to 80% in
the future. Given that power dissipation is a critical parameter in
today's electronic systems, the use of optics to carry data to and
from VLSI chips is an attractive option if it can be done at a low
enough power. To meet future interconnect scaling requirements,
optical output devices need to have energies of ~10 fJ/bit for I/O.
This places a huge constraint on the capacitance of photodetectors,
which form the receiving front end of optical interconnect links. We
estimate that photodetector capacitances of the order of 1 fF are
required. These numbers are achievable for small area photodetectors
fabricated entirely in a Silicon CMOS process that are directly
integrated with the receiving circuitry at the transistor level.

This talk will present our work on the design, fabrication,
characterization, and system level demonstrations of various Silicon
photodetector devices. First we will describe the characterization of
CMOS compatible detectors fabricated in a commercial Silicon on
Sapphire (SOS) CMOS process. Detector response times of ~ 35 ps have
been measured, and devices have capacitance as low as ~ 4 fF. Next,
these photodetectors are integrated with additional circuitry to
implement optically triggered sampler circuits on chip. These
circuits enable us to form a high speed oscilloscope that can measure
high bandwidth analog signals on-chip. We demonstrate the complete
capture of a 20 GHz on-chip signal, and precise measurement of skew
between two separate chip locations. Finally, we present the design
of nano-scale photodetectors fabricated on a Silicon-on-Oxide
platform. These detectors have physical dimensions of the order of
150 nm, and are integrated with optical dipole antennas to resonantly
enhance responsivity. We measure response times of ~2 ps from
nano-scale MSM photodetectors fabricated on this platform. Such
sub-wavelength scale photodetectors offer the promise of
optoelectronic integration at the scale of transistor dimensions, and
coupled with resonantly enhanced detection techniques, would result
in significant power, speed, and area gains.

https://mailman.stanford.edu/mailman/listinfo/ee-students

Eun Ji Kim's Dissertation Defense

Interface and Defect Study of High Permittivity Dielectrics on Si and III-V semiconductors

Eun Ji Kim

Advisors: Prof. Paul C. McIntyre in Materials Science and Engineering
Prof. Krishna C. Saraswat in Electrical Engineering
 
Date: Thursday, Mar. 19, 2009
Time: 2:00 PM (Refreshments served at 1:45 PM)
Location: Packard Bldg. Rm. 202
 
     In an effort to decrease electronic device dimensions and improve device performance, high permittivity dielectrics have been introduced to metal-oxide-semiconductor field effect transistors (MOSFETs). Even though replacing SiO2 with high permittivity dielectrics enabled aggressive device scaling, however, the introduction of new materials gave rise to fundamental problems that could lead to device performance degradation, such as reduction of the effective carrier channel mobility and threshold voltage instabilities. Unsatisfied dangling bonds at the interface of the high permittivity dielectrics and Si, intrinsic and extrinsic point defects in high permittivity dielectrics, and remote phonon scattering are believed to cause degradation of device performance. To understand the limitations to the performance of MOSFETs with high permittivity dielectrics, it is critical to probe phonon modes and defect states directly in high-k dielectrics.
     Inelastic electron tunneling spectroscopy (IETS) is employed to study soft phonon modes and defect states in HfO2 grown by atomic layer deposition (ALD) on Si. Observed spectral features suggest that monoclinic- and tetragonal- HfO2 vibrational modes exist in the annealed HfO2 while crystalline HfO2 vibrational modes are not detected in the as-deposited samples, consistent with selective area electron diffraction analysis. In addition to soft phonon modes of HfO2, changes in amplitude and energy of spectral features were observed as the bias condition changes. We attribute these features to defect-related states in HfO2 and analyze them in terms of electron energy states in the HfO2 bandgap and reported oxygen vacancy states in HfO2.
     For further device scaling, III-V compound semiconductors are receiving increasing attention for channel replacement in the metal-oxide-semiconductor (MOS) technology beyond 22 nm node because of their high intrinsic electron mobility. Unlike SiO2 that exhibits excellent passivating properties on Si with low interface state densities, there typically exists a large density of defect states at the interface of III-V semiconductors and their native oxides. Previous research on GaAs showed that less than 1 % of a monolayer of chemisorbed O2 can pin the Fermi level at the semiconductor surface. Therefore, suppressing oxidation of the III-V semiconductors' surface prior to and during gate dielectric deposition could be essential to achieving device performance superior to that of silicon in nanoscale devices. Several different approaches have been demonstrated to prepare III-V semiconductor-based MOS devices. However, previously attempted methods resulted in frequency-dependent flat band voltage (Vfb) shift, charge trapping in the dielectrics and a relatively high density of interface trap states, possibly from unintentional oxidation of the III-V channel.
     We used In0.53Ga0.47As (100) channels that were capped with an arsenic layer after channel epitaxial growth to avoid III-V oxidation during exposure of the samples to air. The As capping layer was thermally desorbed in-situ in a load-locked ALD reactor prior to Al2O3 gate dielectric deposition. By preventing subcutaneous oxidation of the channel surface, we obtained unpinned Al2O3/In0.53Ga0.47As interfaces with a low density of interface states. The C-V characteristics show a hysteresis of less than 40 mV and relatively small frequency dispersion in accumulation. The surface potential swing (0.44~1.2 eV) calculated using the Berglund integral suggests the absence of a high density of midgap interface states. The observation of near-ideal flat band voltage values for Pt- and Al-electroded MOS capacitors indicates the absence of a significant interface dipole. The temperature-independence of the frequency dispersion of the accumulation capacitance and its scaling with measurement frequency are consistent with tunneling of carriers into defects in the Al2O3 layer, border traps. This also indicates a low interface state density for these devices.
 

Annual Nanoprobes Workshop at Stanford, April 24. Register now.

Dear SNF Labmembers,

On Friday April 24, Stanford's Center for Probing the Nanoscale will
present its 5th Annual Nanoprobes Workshop, on Stanford campus at the
Bechtel Conference Center. Ten outstanding speakers will describe
cutting-edge developments in imaging nanoscale electronic, magnetic,
optical, and chemical phenomena. This will be followed by a
student/postdoc poster session. You and your colleagues are warmly
invited to attend the workshop. Students are encouraged to present
posters -- we typically have many industry attendees who appreciate
having students explain their exciting work.

The website is open for registration. Details about registration and
speakers are below. Also see attached program.

Questions:
Laraine Lietz-Lucas, lietz@stanford.edu

Best wishes,
David Goldhaber-Gordon
Deputy Director, Center for Probing the Nanoscale, an NSF Nanoscale
Science and Engineering Center

Details:

Registration http://www.stanford.edu/group/cpn/research/anworkshop_reg.html

Registration Fee Structure:

Industry - $100
Academic and Government (except CPN Investigators) - $50
Community College, K-12, and Museum Personnel - $25
Students and CPN investigators are free but must register

Speakers:
Bob Westervelt, Harvard University
"Imaging Quantum Devices"
Dmitri Basov, University of California, San Diego
"Infrared Nano-Scopy of Complex Materials"
Sergei Kalinin, Oak Ridge National Laboratory
"Deciphering Nanoscale Interactions: Artificial Neural Networks and
Scanning Probe Microscopy"
Dawn Bonnell, University of Pennsylvania
"Beyond Structure: Probing Complex Properties with Subnanometer Resolution"
Sasha Balatsky, Los Alamos National Laboratory
"Dirac Materials"
Alex de Lozanne, University of Texas, Austin
"Nanocharacterization with Scanning Probes"
Matthias Bode, Argonne National Laboratory
"Imaging Non-Collinear Magnetic Nanostructures with Atomic Resolution"
Ophir Auslaender, Stanford University
"Probing Microscopic and Dynamical Properties of Superconducting
Vortices by Vortex Dragging"
Joachim Stöhr, SLAC National Accelerator Laboratory
"X-Ray Studies of the Ultrafast Magnetic Nanoworld"
Dan Rugar, IBM Almaden Research Center
"Nanoscale MRI – The Quest for a Molecular Structure Microscope"

-----------------------------------------------------------------
David Goldhaber-Gordon goldhaber-gordon@stanford.edu
Associate Professor of Physics davidg@post.harvard.edu
and Deputy Director, (permanent forwarding)
Center for Probing the Nanoscale
www.goldhaber-gordon.com
Stanford University
www.stanford.edu/group/cpn/
(650) 725-2047 (lab) (650) 724-3709 (office)

Address for letters or packages: Administrative Associate:
David Goldhaber-Gordon Roberta Edwards
Geballe Laboratory for Advanced Materials McCullough, Rm. 338
McCullough Building, Room 346 Phone: (650) 723-8028
476 Lomita Mall Fax: (650) 724-3681
Stanford, CA 94305-4045 email:
redward@stanford.edu

seminar: Baris Cagdaser - Monday March 16 3-4pm CIS 101X

===================================================================
Resonant Circuits for Low Voltage Electrostatic Drive and Position Sensing
===================================================================

-----------------------
Monday, March 16, 2009
CIS 101X 3:00-4:00pm
-----------------------

-----------------------------------
Baris Cagdaser
Senior Integrated Circuits Designer
InvenSense, Sunnyvale, CA
-----------------------------------

Abstract
---------
This talk presents a single MEMS electrostatic interface circuit that
does not require high voltage electronics, but does provide high
voltage actuation, position sensing, and extends the range of
parallel-plate actuators.
Electrostatic actuation finds widespread use in micromechanical
systems. Despite being simple in implementation, achieving a
sufficiently large force is often challenging. Increasing the
actuator voltage results in increased force, but requires special
interfaces with high voltage electronics. Furthermore, position
feedback is commonly used to control the dynamic response of the
actuator. In principle, the position dependent actuation capacitance
can be used for sensing. But, in practice, measuring this capacitance
is challenging due to small levels of signal and large feedthrough
from the drive system. So, most actuators need separate sense
electrodes as well as circuit techniques such as time division
multiplexing.
The core of the proposed circuit is an electrical RLC tank formed by
the actuation capacitor and an inductor. When driven at its
electrical resonance, the tank amplifies the voltage across the
actuator capacitor. So, the actuation voltage becomes much higher
than the drive signal provided by electronics. The prototype
implementation uses only a 4Vpeak drive signal to actuate a MEMS
mirror that requires 45VDC under conventional voltage control. Since
the actuator capacitor is position dependent, achieving the maximum
amplification requires an oscillator circuit that automatically
follows the tank's electrical resonance frequency as the actuator
moves. So, the actuator motion translates the oscillator frequency,
which is now used to measure the MEMS displacement in the same
interface circuit. Finally, the position dependent nature of the tank
also increases the range of parallel-plate actuators by providing
inherent position feedback and changing the pull-in behavior.

Biography
----------
Baris Cagdaser received his BS degree from the Middle East Technical
University in Ankara, Turkey, where he worked with Prof. Tayfun Akin
on MEMS capacitive ice detectors. During his PhD studies at the
University of California at Berkeley, he worked with Prof. Bernhard E.
Boser focusing on MEMS interface electronics. Specifically, he
developed a low voltage electrostatic interface for electrostatic
actuation and position sensing. This circuit was used for the
positioning of MEMS micro-mirrors. Since earning his PhD degree in
2005, Baris Cagdaser has been with InvenSense, a Silicon Valley MEMS
start-up company, as a Senior IC Designer working on integrated
interface electronics for MEMS inertial sensors.

Found USB Stick Last Friday at 5:00P Outside Room 126

A concerned labmember found a USB stick last Friday outside room 126 of the CIS Building.  If it’s yours please come by my cubicle and be prepared to describe it.

 

Maureen

 

Maureen Baran

Stanford Nanofabrication Facility

Lab Services Administrator

mbaran@stanford.edu

650-725-3664

 

Highly-doped 4" p-type Si wafer

Dear Labmembers,

Does anyone have highly-doped (<0.01 ohm-cm) 4" p-type Si wafers? I wonder if any of you could provide me two of them. Thank you.

Sincerely,
Yoonyoung Chung

Lost Notebook and Wafers

Hi Labmembers:
I lost my lab notebook and some processed wafers in a wafer box
today (3/6, Friday). The notebook has my login name (jtsai) on, and the
wafer box only has some lot numbers on it. If you took them by mistake
or see them in the lab, could you please let me know. Thank you a lot.

Regards,
JrHung
Kumetrix Inc.

Refractometer

Hi,

I was wondering if anyone has a refractometer in their lab that I could use to measure the refractive index of both solids and liquids.  If not, perhaps someone may know where I can find one.

Thanks,
Chris Lueth

Special Process Clinic: Monday, 3/9, 2-4 pm

Hi all --

There will be a special process clinic this Monday, March 9, from 2-4
pm, in the cubicle area near Maureen's office. Keith Best from ASML
will be there, dispensing wisdom he's collected from working with and in
a variety of fab areas. And Bill Martin, from Compugraphics, will be on
hand from 3 pm to answer questions about masking and layouts. So, bring
your process flows and your layouts. It'll be fun.

Your SNF Staff

--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu

Re: Problem p5000etch SNF 2009-03-05 19:41:48: power off

Eric restarted the system. System looks ok. Ran 4 wafers through Ch.B with no problems.

Re: Comment p5000etch SNF 2009-03-05 20:33:31: power restored

System looks ok. Ran 4 wafers through Ch.B with no problems.

Comment p5000etch SNF 2009-03-05 20:33:31: power restored

It's running, and back under vacuum. All three chambers are online.

Problem p5000etch SNF 2009-03-05 19:41:48: power off

power is off somehow, cann't use the system.

Soitec wafers wanted

Hi all,

I'd like to get hold of a few Soitech wafers (any device
thickness/doping is OK) for some experiments. If anyone has a few
spare (can trade for something!) or knows of a vendor that will sell a
few, it would be greatly appreciated!

Thanks much,
Dan.

ASML Customer Workshop at SNF - Tuesday, March 31, 2009 - 12 noon to 5 pm

On behalf of ASML and Keith Best, you are invited to their Customized Imaging Solutions customer workshop on Tuesday, March 31, 2009 from 12 noon to 5 pm.  In order to get a proper count for the lunch ASML is providing, please register at:

http://www.surveymonkey.com/s.aspx?sm=fJEcP3GkvBdm3b_2bFqy5Mjg_3d_3d

---

From: ASML CIS [ mailto:michael.pullen@asml.com]
Sent: Wednesday, March 04, 2009 12:37 PM
To: Keith Best
Subject: ASML CIS Customer Workshop at Stanford Nanofabrication Facility (SNF)

 
ASML CIS Customer Workshop at Stanford Nanofabrication Facility (SNF)

    
Please Register to Attend
Agenda
12:00 PM Lunch

1:00 PM Welcome & Introduction - Keith Best (ASML)
1:10 PM MEMS Market and ASML Solutions - Keith Best (ASML)
1:40 PM Recent results from Stanford/ASML - JDA Paul Rissman (SNF)
2:10 PM Canadian Photonics Fabrication Center's approach to patterning - Simon Wingar (CPFC)
2:30 PM GE - ASML small piece handling project - Keith Best (ASML)
2:50 PM Quick-turn device development w/ASML's compound image design software (CID)- Paul Schuele (Sharp)

3:10 PM Coffee Break

3:30 PM ASML CIS demo update - Vinny Pici (ASML)
4:00 PM TFH market and ASML solutions - Keith Best (ASML)
4:30 PM Leveraging Lithography Toolsets in a Development Foundry-SVTC - Mary Zawadzki(SVTC)

5:00 PM Close

Please respond by filling out the registration form.
Go to Registration Form


Date: Tuesday, March 31st
Time: 12:00 PM - 5:00 PM
Location: SNF Auditorium, Paul Allen Center for Integrated Systems (CIS) Extension
Visitor Information

© Copyright 2009 (ASML) All rights reserved | ASML Netherlands B.V., De Run 6501, 5503 LA Veldhoven, The Netherlands
  Legal Terms and Conditions | Privacy Policy

-- The information contained in this communication and any attachments is confidential and may be privileged, and is for the sole use of the intended recipient(s). Any unauthorized review, use, disclosure or distribution is prohibited. Unless explicitly stated otherwise in the body of this communication or the attachment thereto (if any), the information is provided on an AS-IS basis without any express or implied warranties or liabilities. To the extent you are relying on this information, you are doing so at your own risk. If you are not the intended recipient, please notify the sender immediately by replying to this message and destroy all copies of this message and any attachments. ASML is neither liable for the proper and complete transmission of the information contained in this communication, nor for any delay in its receipt.

RE: Diffusion cleaning (or some cleaning) for 12 inch Silicon wafers

Noel Technologies in Campbell, CA

www.noeltech.com

Regards,
Alissa

Alissa M. Fitzgerald, Ph.D.
Managing Member

A.M. Fitzgerald & Associates, LLC
655 Skyway Rd. Suite 118
San Carlos, CA 94070
+1 (650) 592-6100 x101 phone
+1 (650) 592-6111 fax
www.amfitzgerald.com

> -----Original Message-----
> From: Gaurav Thareja [mailto:gthareja@stanford.edu]
> Sent: Tuesday, March 03, 2009 2:21 PM
> To: labmembers
> Subject: Diffusion cleaning (or some cleaning) for 12 inch
> Silicon wafers
>
> Dear lab-mates
>
> We are interested to get diffusion clean for a few 12 inch
> Silicon wafers. Please let us know, if there is a facility or
> company who can do it for us.
>
> thanks
> ~gaurav

Diffusion cleaning (or some cleaning) for 12 inch Silicon wafers

Dear lab-mates

We are interested to get diffusion clean for a few 12 inch Silicon wafers. Please let us know, if there is a facility or company who can do it for us.

thanks
~gaurav

Eun Ji Kim's Ph.D. Oral Exam

Interface and Defect Study of High Permittivity Dielectrics on Si and III-V semiconductors

 

Eun Ji Kim

Advisors: Prof. Paul C. McIntyre in Materials Science and Engineering

Prof. Krishna C. Saraswat in Electrical Engineering

 

Date: Thursday, Mar. 19, 2009

Time: 2:00 PM (Refreshments served at 1:45 PM)

Location: Packard Bldg. Rm. 202

 

    

In an effort to decrease electronic device dimensions and improve device performance, high permittivity dielectrics have been introduced to metal-oxide-semiconductor field effect transistors (MOSFETs). Even though replacing SiO₂ with high permittivity dielectrics enabled aggressive device scaling, however, the introduction of new materials gave rise to fundamental problems that could lead to device performance degradation, such as reduction of the effective carrier channel mobility and threshold voltage instabilities. Unsatisfied dangling bonds at the interface of the high permittivity dielectrics and Si, intrinsic and extrinsic point defects in high permittivity dielectrics, and remote phonon scattering are believed to cause degradation of device performance. To understand the limitations to the performance of MOSFETs with high permittivity dielectrics, it is critical to probe phonon modes and defect states directly in high-k dielectrics.

Inelastic electron tunneling spectroscopy (IETS) is employed to study soft phonon modes and defect states in HfO₂ grown by atomic layer deposition (ALD) on Si. Observed spectral features suggest that monoclinic- and tetragonal- HfO₂ vibrational modes exist in the annealed HfO₂ while crystalline HfO₂ vibrational modes are not detected in the as-deposited samples, consistent with selective area electron diffraction analysis. In addition to soft phonon modes of HfO₂, changes in amplitude and energy of spectral features were observed as the bias condition changes. We attribute these features to defect-related states in HfO₂ and analyze them in terms of electron energy states in the HfO₂ bandgap and reported oxygen vacancy states in HfO₂.

For further device scaling, III-V compound semiconductors are receiving increasing attention for channel replacement in the metal-oxide-semiconductor (MOS) technology beyond 22 nm node because of their high intrinsic electron mobility. Unlike SiO₂ that exhibits excellent passivating properties on Si with low interface state densities, there typically exists a large density of defect states at the interface of III-V semiconductors and their native oxides. Previous research on GaAs showed that less than 1 % of a monolayer of chemisorbed O₂ can pin the Fermi level at the semiconductor surface. Therefore, suppressing oxidation of the III-V semiconductors' surface prior to and during gate dielectric deposition could be essential to achieving device performance superior to that of silicon in nanoscale devices. Several different approaches have been demonstrated to prepare III-V semiconductor-based MOS devices. However, previously attempted methods resulted in frequency-dependent flat band voltage (V_fb) shift, charge trapping in the dielectrics and a relatively high density of interface trap states, possibly from unintentional oxidation of the III-V channel.

We used In_0.53Ga_0.47As (100) channels that were capped with an arsenic layer after channel epitaxial growth to avoid III-V oxidation during exposure of the samples to air. The As capping layer was thermally desorbed in-situ in a load-locked ALD reactor prior to Al₂O₃ gate dielectric deposition. By preventing subcutaneous oxidation of the channel surface, we obtained unpinned Al₂O₃/In_0.53Ga_0.47As interfaces with a low density of interface states. The C-V characteristics show a hysteresis of less than 40 mV and relatively small frequency dispersion in accumulation. The surface potential swing (0.44~1.2 eV) calculated using the Berglund integral suggests the absence of a high density of midgap interface states. The observation of near-ideal flat band voltage values for Pt- and Al-electroded MOS capacitors indicates the absence of a significant interface dipole. The temperature-independence of the frequency dispersion of the accumulation capacitance and its scaling with measurement frequency are consistent with tunneling of carriers into defects in the Al₂O₃ layer, border traps.  This also indicates a low interface state density for these devices.