Seminar Reminder: Dr. Paul J. Hung, CellASIC Corporation 4-5pm Allen 101X

Hi all,

Interesting seminar next Tuesday, January 31, 4-5pm @ Allen 101X Auditorium.

Speaker: Dr. Paul J. Hung, CellASIC Corporation

Topic: Polymer MEMS for Cell-based Microphysiological Platform

Abstract: 

In the post-­‐genomic era, the next waves of innovation has centered on understanding and utilizing living cells. Physiologic cells are 3D individuals receiving dynamic cues from their perspective microenvironment in order to perform properly; however, current cell-­‐based studies are dominantly conducted on static 2D format, leaving a large gap between research findings and clinical applications. Polymer Micro-­‐Electrical-­‐Mechanical Systems (MEMS) could potentially bridge the gap by providing a more clinically relevant platform to manipulate living cells. Polymer has attractive properties such as biocompatibility, gas permeability, and well-­‐ understood surface chemistry. MEMS offer the ability to probe into the time and geometric scale similar to those found in the physiologic cellular microenvironments. The established manufacturing infrastructure further reduces the level of resource investment in project development. In this talk, I will first define the roles for each component of Polymer MEMS in creating cell-­‐based microphysiological platforms. A systematic method to design physiologic-­‐ relevant cell-­‐based circuitry will then be presented. Robust manufacturing processes to implement the design on a user-­‐friendly format will be discussed. A toxicity and metabolism screening platform capable of maintaining metabolic functions of liver cells for over 4 weeks will be used as an example. Finally, potential applications of Polymer MEMS for personalized cell diagnosis and therapy will be mentioned. 

Short Bio:

Paul J Hung co-­‐founded CellASIC Corporation in 2005 to develop and commercialize advanced cell-­‐based platforms with Polymer MEMS technology. He received his B.S. degree in Electrical Engineering from National Taiwan University in 1999, and Ph.D. from University of California at Berkeley in Electrical Engineering in 2005. Dr. Hung's research interests include polymer MEMS, biosensors, and platform engineering with the aims to develop the next generation bio-­‐ instrumentation, as well as personalized biomedical devices. 

--

Jose Padovani

Graduate Student

Electrical Engineering Department

Stanford University

[Reminder] MSE PhD Dissertation Defense: Marika Gunji (Tomorrow, 2PM)

Nanostructured SiGe and Ge for Future Electronic Devices

 

Marika Gunji

Department of Materials Science and Engineering

Advisor: Prof. Paul C. McIntyre

Monday January 30^th 2012, 2PM (Refreshments at 1:45PM)

Location: CIS-X 101 Allen Auditorium

(http://cis.stanford.edu/directions/)

 

As the packing density of silicon (Si) integrated circuits (IC) increases, scaling requirements are becoming severe. Two approaches are considered to be effective to continue dimensional scaling. One is to alter the device layer so that it is a semiconductor other than silicon. Silicon-germanium (SiGe) and germanium (Ge) are suitable candidates because of their greater carrier mobilities than Si and their process compatibility with Si substrates. Another approach is to change the device or circuit structures so that there is less power consumption and better performance for higher device packing densities in ICs. Nanoscale structures such as ultra-thin semiconductor-on-insulators or nanowires can be incorporated in future transistors.

The presentation will focus initially on synthesis of highly compressively strained SiGe-on-insulator (SGOI) substrate fabrication. The strain relaxation mechanisms in highly compressively-strained (0.67% ~ 2.33% biaxial strain), thin SGOI structures with Ge atomic fraction ranging from 0.18 to 0.81 will be described. SGOI layers (8.7 nm ~ 75 nm thickness) were fabricated by selective oxidization of Si from compressively strained SiGe films epitaxially grown on single crystalline Si-on-insulator (SOI) layers. After high temperature oxidation annealing, ~ 30% of the observed strain relaxation can be attributed to formation of intrinsic SFs and the remaining strain relaxation to stress-driven buckling of the SiGe layers.

The presentation will also discuss the path to obtain higher-k dielectrics on Ge metal-oxide-semiconductor (MOS) devices. To obtain high gate capacitance density dielectrics on high-mobility Ge channels, one solution is to interpose a large energy band gap (E_g) insulator with moderate k as an interface layer between a higher-k dielectric and the channel, since higher-k dielectrics tend to have small E_g. Al₂O₃ layers (k ~ 8) can have stable interfaces with Ge and a large band gap. On the other hand, TiO₂ can achieve a much higher k value (~ 60) when in the rutile crystalline phase, but its conduction band offset with Ge is less than 1 eV. TiO₂/Al₂O₃ bilayers deposited on Ge(100) by ALD can achieve low interface trap density with small leakage current after post-metal forming gas anneal. From measurements performed on MOS capacitors, the maximum capacitance at a given frequency increases after the 450 °C forming gas anneal, indicating that the dielectric constant of TiO₂ increased to ~50 after annealing. Consistent with these results, TEM datae indicate that the ALD-grown TiO₂ phase had predominantly transformed to the rutile phase after annealing.

In order to measure the channel transfer characteristics for this TiO₂ (7.5 nm)/Al₂O₃ (2.5 nm)/Ge(100) stack, pMOSFETs with long channels (L_g = 2 – 30 um) were fabricated. The devices show a subthreshold swing of 115 mV/dec and an on-state current of 60 mA/mm. Measured peak hole mobility reaches 370 cm²/Vs, which suggests the feasibility and potential of TiO₂/Al₂O₃/Ge gate stacks for high performance MOSFETs.

--
---------------------------------
Marika Gunji

PhD Candidate
McIntyre Group
Department of Materials Science and Engineering
Stanford University
E-mail: gunjim@stanford.edu

--
---------------------------------
Marika Gunji

PhD Candidate
McIntyre Group
Department of Materials Science and Engineering
Stanford University
E-mail: gunjim@stanford.edu

SNF Renovation Update

Dear Labmembers --

After 6 weeks of extended shutdown and construction, we are very pleased to report that the renovation is going extremely well.  The construction crew is knowledgeable, professional, and know our concerns -- they worked extra shifts and weekends to help us minimize the shutdown time and impact to labmembers' research.  Main construction work is done and has passed most of the inspections with the County. 

There are, however, still a few inspections outstanding, so until these are done, we won't have a definite date as to when the lab will be reopened for use.  We will keep everyone posted as we get more information.  Please check out the behind-the-scenes photos of the construction, links on the SNF website (see News links.)

Your SNF staff

--  Mary X. Tang, Ph.D. Stanford Nanofabrication Facility Paul G. Allen Room 136, Mail Code 4070 Stanford, CA  94305 (650)723-9980 mtang@stanford.edu http://snf.stanford.edu 

Seminar - Dr. Paul J. Hung, CellASIC Corporation

Hi all,

Interesting seminar next Tuesday, January 31, 4-5pm @ Allen 101X Auditorium.

Speaker: Dr. Paul J. Hung, CellASIC Corporation

Topic: Polymer MEMS for Cell-based Microphysiological Platform

Abstract: 

In the post-­‐genomic era, the next waves of innovation has centered on understanding and utilizing living cells. Physiologic cells are 3D individuals receiving dynamic cues from their perspective microenvironment in order to perform properly; however, current cell-­‐based studies are dominantly conducted on static 2D format, leaving a large gap between research findings and clinical applications. Polymer Micro-­‐Electrical-­‐Mechanical Systems (MEMS) could potentially bridge the gap by providing a more clinically relevant platform to manipulate living cells. Polymer has attractive properties such as biocompatibility, gas permeability, and well-­‐ understood surface chemistry. MEMS offer the ability to probe into the time and geometric scale similar to those found in the physiologic cellular microenvironments. The established manufacturing infrastructure further reduces the level of resource investment in project development. In this talk, I will first define the roles for each component of Polymer MEMS in creating cell-­‐based microphysiological platforms. A systematic method to design physiologic-­‐ relevant cell-­‐based circuitry will then be presented. Robust manufacturing processes to implement the design on a user-­‐friendly format will be discussed. A toxicity and metabolism screening platform capable of maintaining metabolic functions of liver cells for over 4 weeks will be used as an example. Finally, potential applications of Polymer MEMS for personalized cell diagnosis and therapy will be mentioned. 

Short Bio:

Paul J Hung co-­‐founded CellASIC Corporation in 2005 to develop and commercialize advanced cell-­‐based platforms with Polymer MEMS technology. He received his B.S. degree in Electrical Engineering from National Taiwan University in 1999, and Ph.D. from University of California at Berkeley in Electrical Engineering in 2005. Dr. Hung's research interests include polymer MEMS, biosensors, and platform engineering with the aims to develop the next generation bio-­‐ instrumentation, as well as personalized biomedical devices. 

--

Jose Padovani

Graduate Student

Electrical Engineering Department

Stanford University

electrochemical CV measurement

Hi Labmembers,

Does anyone know where I might be able to do an electrochemical capacitance-voltage profiling measurement? I'm looking to characterize a III-V film on a heavily doped n-type Si substrate.

Thanks,
Angie

Venture Clinic Today, Tuesday, Allen 101, 4 pm

Dear labmembers --

Thinking about starting up a company while you're waiting for the lab
renovation to end? Shahin Farschi (Lux Capital) and Gavin McCraley
(Morrison Foerster) will be here to host an open discussion and answer
questions about startups. The Venture Clinic will start at 4 pm,
Tuesday, Jan. 24, in Allen 101.

--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
Paul G. Allen Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu

MSE PhD Dissertation Defense: Naga Phani Aetukuri - 6th Feb 3pm CIS-X 101

Department of Materials Science & Engineering

University PhD Dissertation Defense

 

Electrically-Triggered Metallization in Single-Crystal Vanadium Dioxide Thin Film Heterostructures

 

Naga Phani Aetukuri

 

Research Advisor: Professor James Harris

Co-Advisor: Professor Stuart Parkin

Co-Advisor: Professor Paul McIntyre

 

February 6, 2012 @ 3:00 PM

(Refreshments will be served starting at 2:45 PM)

 

Location: Paul G. Allen Auditorium (CISX 101)
http://cis.stanford.edu/directions

 

 

Vanadium dioxide (VO₂) is metallic at high temperatures but undergoes a metal to insulator transition (MIT) below ~340 K in bulk crystals that is generally attributed to electron-electron correlation effects.  This transition can also be engendered by the application of modest electric fields, several orders of magnitude below the electric breakdown field, making this phenomenon potentially useful for two or three terminal switches, depending on its speed and origin.

 

We have used pulsed laser deposition to prepare epitaxial single-crystalline thin films of VO₂ that show a sharp change in resistance at the MIT for films as thin as 10nm.  We find that strain induced by underlying layers can modify the transition temperature of these films.  For example, on TiO₂ (001) single-crystal substrates, the transition temperature is reduced to ~290 K, whereas by growing similar films on RuO₂ buffers layers the MIT can be increased up to ~335 K. 

 

A combination of electron-beam and optical lithography was used to fabricate lateral two-terminal nano-devices from VO₂ films deposited directly on TiO₂ substrates.   We have observed reversible and reproducible transitions triggered by electric-field but with a delay time varying from as long as 10 ns to as short as 500 ps.  The delay time is found to decrease with increasing electric field and temperature.  We discuss whether these results indicate the transition is dominated by electronic or by Joule heating effects. In vertical structures with a metallic RuO₂ bottom electrode, we have used a current-sensing atomic force microscope to probe the electric-field-induced MIT in much smaller volumes of VO₂.  Reversible switching between insulating and metallic states was observed at modest electric fields for VO₂ layers as thin as 20 nm. These results demonstrate the possibility of triggering an MIT at low voltages and, therefore, at low energies, which is essential for device applications.

Blue Tape

Hi All,

Does anyone have some blue tape to spare?  I can pay you with a modicum of chocolate for your generosity.  I would appreciate it if I could have the tape by tomorrow afternoon.

Cheers,

Vijay

(650) 453-8564

Venture Clinic, Tues, 1/24 4 pm, Allen 101

Dear Labmembers -

Interested in starting a company, joining a startup, or just learning more
about starting, funding, and raising money for fledgling technology
companies? Join VC Clinic where Shahin Farshchi, Principal at Lux Capital
and Gavin McCraley, Of Counsel at law firm Morrison Forrester discuss and
answer questions on mechanics and challenges of creating and growing
technology companies. Venture Clinic will be held at 4PM Tuesday, January
24th in Allen 101.

--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
Paul G. Allen Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu

Oral Exam Announcement: Soogine Chong

Stanford University PhD Oral Defense - Department of Electrical Engineering
Title: Design and Fabrication of Nanoelectromechanical (NEM) Relays Integrated with CMOS
Speaker: Soogine Chong
Advisor: Professor H.-S. Philip Wong

Date: Friday, January 20, 2012
Time: 10:00 AM (Refreshments served at 9:45 AM)
Location: Paul G. Allen Auditorium (Formerly CISX-101)

Abstract:
CMOS scaling following Moore's Law has resulted in a dramatic increase in computing power over the decades. This was possible by scaling down the CMOS transistors, both in dimensions and voltage. However, continuous voltage scaling is becoming increasingly difficult because of the increase in subthreshold leakage. This increase is inevitable with threshold voltage scaling, since the subthreshold slope is theoretically limited to be larger than 60 mV/dec. Nanoelectromechanical (NEM) relays are promising devices to overcome this voltage scaling issue because of their sharp on/off transition characteristics and zero off-state leakage. However, these devices have long switching times due to their long mechanical delays. By combining NEM relays with CMOS, it is possible to capitalize on the benefits of each technology.

In this talk, I propose a novel NEM-CMOS SRAM cell design, followed by an experimental demonstration of the fabrication of NEM relays and their integration with CMOS. In the proposed NEM-CMOS SRAM cell, NEM relays replace the pull-down NMOS transistors of a conventional six-transistor CMOS SRAM cell. Simulations show that this hybrid cell has an increased stability and a lower leakage compared to those of a conventional CMOS SRAM cell, without the long mechanical delay of the NEM relay limiting the performance. Despite these advantages, this circuit has not yet been experimentally demonstrated. As an initial step toward the demonstration, I first demonstrate the fabrication of NEM relays without CMOS in two different versions: optically patterned scaled-up devices and e-beam patterned scaled-down devices. With the scaled down devices that have a CMOS-compatible fabrication process, I show an on-chip CMOS inverter successfully driving a NEM relay at the same supply voltage, demonstrating the feasibility of NEM-CMOS integration.

--
Soogine Chong
Stanford University
PhD candidate in Electrical Engineering
e-mail: sgchong@stanford.edu
mobile: +1-650-804-8556

Re: transparent conductive substrate

Hi Xi,

We used to buy 4" 1mm thick corner glass wafers coated by ITO for
several times in the past. The surface resistance was around 20 ohm/sq.
The vendor was TFD (Thin Film Devices). It's about 5 years passed since
our last purchase, but they are still in business, apparently:
http://www.tfdinc.com/

Good luck,
Sergei

On 1/14/2012 6:19 PM, Xi Xie wrote:
> Hi All,
> I need a transparent conductive substrate/film/cable/tape, something like Si wafer or Copper tape but need to be transparent and have good conductivity. Anyone have any idea anything like that and I can readily buy?
> Also I try to deposite Au on glass slide but the conductivity is low. Any one have better idea of how to do that? Thanks!
>
> Best,
> Xi

kapton tape

Hi all,

I'm trying to prepare some samples for Tom Carver's lab and need some kapton tape (probably ~20cm). Does anyone have some I could use? It would be greatly appreciated.

Thanks,

Scott

Invitation to Raith / Stanford Advanced Lithography Workshop - February 15, 2012

Greetings Lab Members and the Raith Ebeam Lithography Community:

I am pleased to announce, and to invite you to join us for an Advanced Nanolithography Workshop. This will be held on Wednesday February 15, 2012 with additional demonstrations and application specific tutorials to be held the following day.  You are requested to register using the links below.

Thank you for your support!

James Conway

Stanford's RAITH150 system has just been upgraded with Raith's unique Fixed Beam Moving Stage (FBMS) capability.  In this context, Raith and the Stanford Nanofabrication Facility cordially invite you to attend the Advanced Nanolithography Workshop.  This one day workshop will be dedicated to advanced patterning techniques that have been implemented by Raith for both electron and ion beam lithography to enhance nanoscale fabrication beyond traditional vector scan patterning. Please use the link below to automatically register for the workshop. As space is limited, we hope that you can confirm as soon as possible. When: Wednesday February 15, 2012 Where: Allen Building Auditorium (ALLEN 101X), Stanford University Time: 9:30 AM - 4:00 PM Click Here to Register Agenda 9:30 AM - 10:00 AM Gather, greet and meet over coffee and light snack. 10:00 AM - 11:00 AM Zero Stitching Error Lithography by Raith Fixed Beam Moving Stage (FBMS) - Part I - For Nanophotonics, Plasmonics, and More Jason E. Sanabia, Ph.D., President & CEO, Raith USA, Inc. 11:00 AM - 12:00 PM Application of FBMS towards nanophotonics/plasmonics External Guest TBD 12:00 PM - 1:00 PM Lunch served (soup, sandwiches, salads) 1:00 PM - 2:00 PM  Zero Stitching Error Lithography by Raith Fixed Beam Moving Stage (FBMS) - Part II - Advanced Periodic Patterning Jason E. Sanabia, Ph.D., President & CEO, Raith USA, Inc. 2:00 PM - 3:00 PM Ion Beam Lithography with Advanced Patterning Modes, Joseph Klingfus, Ph.D., Applications Scientist and Project Manager for the Stanford RAITH150, Raith USA, Inc. 3:00 PM - 4:00 PM Open discussions

 

Sent to:jwc@snf.stanford.edu If you prefer not to receive future e-mails of this type, click here

Sent By: Raith USA, Inc. 2805 Veterans Highway Suite 23 Ronkonkoma New York 11779 United States

To view as a web page click here.

EE PhD Oral Examination -- Kelley Rivoire, Fri. Jan 20, 2 pm, Nano 232

Stanford University PhD Oral Defense - Department of Electrical Engineering

Title: Nonlinear frequency conversion in III-V semiconductor photonic crystals
Speaker: Kelley Rivoire
Advisor: Jelena Vuckovic

Date: Friday, Jan. 20, 2012
Time: 2 pm (refreshments served at 1:45 pm)
Location: Nano Building, room 232

Abstract:

Nonlinear optical processes provide a physical mechanism for
converting the frequency of light. This allows the generation of
tunable light sources at wavelengths inaccessible with lasers, leading
to a diverse set of applications in fields such as spectroscopy,
sensing, and metrology. To make these processes efficient has
conventionally required relatively exotic materials that are
incompatible with state of the art nanofabrication, resulting in
large-area devices that operate at high optical powers and cannot be
integrated with on-chip optical and electronic circuits.

In this talk, I will show how optical nanocavities, by localizing
light into sub-cubic optical wavelength volumes with long photon
storage times, can greatly enhance the efficiency of nonlinear
frequency conversion processes in III-V semiconductors, while
simultaneously shrinking the device footprint, reducing the operating
power, and providing a scalable on-chip platform. This approach also
enables on-chip quantum frequency conversion interfaces, which are
crucial for the construction of quantum networks. I will first
describe how photonic crystal nanocavities in gallium phosphide can
generate second harmonic radiation with only nanowatts of coupled
optical powers, and efficiency many orders of magnitude greater than
in previous nanoscale devices. We extend this approach to demonstrate
sum-frequency generation in GaP photonic crystal cavities with
multiple cavity modes, as well as broadband upconversion employing
photonic crystal waveguides. I will then discuss how we can integrate
nanocavity-enhanced second harmonic generation with a single quantum
dot to create a single photon source triggered at 300 MHz by a
telecommunication wavelength laser coupled with an external
electro-optic modulator, a simpler and faster configuration than
standard approaches. Finally, I will present the design and
characterization of multi-resonant photonic crystal nanocavities with
large frequency separation that can further reduce the powers of all
of the aforementioned processes.

MSE PhD Dissertation Defense: Marika Gunji (Mon January 30th, 2PM)

Nanostructured SiGe and Ge for Future Electronic Devices

 

Marika Gunji

Department of Materials Science and Engineering

Advisor: Prof. Paul C. McIntyre

Monday January 30^th 2012, 2PM (Refreshments at 1:45PM)

Location: CIS-X 101 Allen Auditorium

(http://cis.stanford.edu/directions/)

 

As the packing density of silicon (Si) integrated circuits (IC) increases, scaling requirements are becoming severe. Two approaches are considered to be effective to continue dimensional scaling. One is to alter the device layer so that it is a semiconductor other than silicon. Silicon-germanium (SiGe) and germanium (Ge) are suitable candidates because of their greater carrier mobilities than Si and their process compatibility with Si substrates. Another approach is to change the device or circuit structures so that there is less power consumption and better performance for higher device packing densities in ICs. Nanoscale structures such as ultra-thin semiconductor-on-insulators or nanowires can be incorporated in future transistors.

The presentation will focus initially on synthesis of highly compressively strained SiGe-on-insulator (SGOI) substrate fabrication. The strain relaxation mechanisms in highly compressively-strained (0.67% ~ 2.33% biaxial strain), thin SGOI structures with Ge atomic fraction ranging from 0.18 to 0.81 will be described. SGOI layers (8.7 nm ~ 75 nm thickness) were fabricated by selective oxidization of Si from compressively strained SiGe films epitaxially grown on single crystalline Si-on-insulator (SOI) layers. After high temperature oxidation annealing, ~ 30% of the observed strain relaxation can be attributed to formation of intrinsic SFs and the remaining strain relaxation to stress-driven buckling of the SiGe layers.

The presentation will also discuss the path to obtain higher-k dielectrics on Ge metal-oxide-semiconductor (MOS) devices. To obtain high gate capacitance density dielectrics on high-mobility Ge channels, one solution is to interpose a large energy band gap (E_g) insulator with moderate k as an interface layer between a higher-k dielectric and the channel, since higher-k dielectrics tend to have small E_g. Al₂O₃ layers (k ~ 8) can have stable interfaces with Ge and a large band gap. On the other hand, TiO₂ can achieve a much higher k value (~ 60) when in the rutile crystalline phase, but its conduction band offset with Ge is less than 1 eV. TiO₂/Al₂O₃ bilayers deposited on Ge(100) by ALD can achieve low interface trap density with small leakage current after post-metal forming gas anneal. From measurements performed on MOS capacitors, the maximum capacitance at a given frequency increases after the 450 °C forming gas anneal, indicating that the dielectric constant of TiO₂ increased to ~50 after annealing. Consistent with these results, TEM datae indicate that the ALD-grown TiO₂ phase had predominantly transformed to the rutile phase after annealing.

In order to measure the channel transfer characteristics for this TiO₂ (7.5 nm)/Al₂O₃ (2.5 nm)/Ge(100) stack, pMOSFETs with long channels (L_g = 2 – 30 um) were fabricated. The devices show a subthreshold swing of 115 mV/dec and an on-state current of 60 mA/mm. Measured peak hole mobility reaches 370 cm²/Vs, which suggests the feasibility and potential of TiO₂/Al₂O₃/Ge gate stacks for high performance MOSFETs.

--
---------------------------------
Marika Gunji

PhD Candidate
McIntyre Group
Department of Materials Science and Engineering
Stanford University
E-mail: gunjim@stanford.edu

LEdit Macro Examples?

Hi all,
I'm trying to use a macro to create a layout in LEdit. I was wondering if anyone had any example macros they could share with me.
Thanks,
Chris

transparent conductive substrate

Hi All,
I need a transparent conductive substrate/film/cable/tape, something like Si wafer or Copper tape but need to be transparent and have good conductivity. Anyone have any idea anything like that and I can readily buy?
Also I try to deposite Au on glass slide but the conductivity is low. Any one have better idea of how to do that? Thanks!

Best,
Xi

NNIN computing facility

All

This is a great resource. please contact Zhiyong for more info.

Art

---------- Forwarded message ----------
From: Zhiyong Zhang
Date: Thursday, January 12, 2012
Subject: NNIN computing facility
To: Artit Wangperawong <artitw@stanford.edu>


Artit,

Stanford is one of the sites of NNIN with computing capabilities. NNIN provides facilities for academic and industrial users. We here at Stanford have a cluster with 512 cores and a large range of software packages, including various ab inito packages such as QMC and various DFT packages. Here is some simple description of the facility at Stanford, http://www.stanford.edu/group/nnin-computing/ and at other sites which have the computing facilities, http://www.nnin.org/nnin_compsim.html. You can also install your own software for your simulations and use the cluster for development purposes.

If you need to access the cluster for your simulations I will be happy to set it up for you. Also if you know of anybody who could benefit from using the cluster, please feel free to pass the word to them also.

Best,

Zhiyong

Fwd: J.A. Woollam WVASE32 Short Course

Please contact Veronica Cockerill at JA Woollam if you are interested in attending.

-------- Original Message --------

Subject:	J.A. Woollam WVASE32 Short Course
Date:	Thu, 12 Jan 2012 14:41:30 -0600
From:	Veronica Cockerill <vcockerill@jawoollam.com>
To:	WoollamMailList@jawoollam.com

Dear J.A. Woollam Customers,

We would like to invite those of you who use our WVASE32 software to the next WVASE32 Data Analysis Fundamentals Short Course. It will be held March 6-9, 2012 at the University of North Carolina Charlotte. I have attached a course description and registration form. If you would like to attend, please fill out the registration form completely and fax or email to me by February 24, 2012. Once I receive your registration form, I will send a confirmation email.

This course will focus on data analysis methods for spectroscopic ellipsometry, using WVASE32 software, with a significant amount of "hands-on" computer time. For this reason, participants should be familiar with WVASE32 software.

NOTE: Many of you use our other data analysis software, CompleteEASE. A course dedicated to WVASE32 will not be of benefit to you if you use CompleteEASE. They are two completely different programs. The next CompleteEASE short course has not been scheduled yet. Once it is, I will notify you of that course. Thank you for your patience.

If you have any questions, please let me know.

Best regards,
Veronica

--

*******************************
Veronica Cockerill
Marketing Coordinator
J. A. Woollam Co., Inc.
645 M Street, Suite 102
Lincoln, NE 68508
vcockerill@jawoollam.com
Phone: (402)477-7501 x101
Fax: (402)477-8214

CVD seminars during Winter Quarter

During the Winter Quarter on Tuesdays at 1:30 pm (except for February 21), I plan to give a series of informal talks on CVD - including epi. The talks will be based on fairly old material, but might provide some useful background for those using or interested in CVD.

The first talk will be on Tuesday, January 10, starting at 1:30 pm, in Allen - 338X.

A (perhaps somewhat overly ambitious) outline based on a previous short course is attached.

Ted