EE PhD Oral Examination - Peter Chen, Friday, January 21, 2011; 2:00pm

Stanford University Ph.D. Dissertation Defense

Title: "Heterogeneous Integration by Dry Parallel Insertion"

Jeng-Wen Peter Chen
Department of Electrical Engineering
Research Advisor: Prof. Roger Howe

Date: Friday, January 21, 2011
Time: 2:00 pm (Refreshments beforehand)
Location: Allen CIS 101X (Auditorium)
http://campus-map.stanford.edu/index.cfm?ID=04-055

Abstract:

Integration of CMOS and MEMS promises systems that are smaller, lighter,
more power-efficient, and higher performance. One approach is
Heterogeneous Integration, which combines MEMS and CMOS from different
substrates, avoiding challenges in co-fabrication. In this talk, I will
present a method for integration of silicon chiplets into target wafer
pockets by a dry, two-step, backside insertion. The precise mechanical
alignment is provided by wafer-embedded guide tabs, giving better than
2.5μm alignment, with zero applied insertion force. The scaling to
higher precision is possible with more precise chiplets. The
"reconstituted" wafer can continue batch wafer processing for further
process flexibility. This process can provide dense and short
interconnections between CMOS and MEMS, as well as provide a generic
method for precise passive alignment of microfabricated parts.