Thank you,
Bei
==============================
Graduate Student
QSL Lab.,EngrII 228
Dept.of Electrical Engineering
University of California
Riverside, CA 92521
Ph.# (951) 827-6275
Fax# (951) 827-2425
http://qsl.ee.ucr.edu/
==============================
Hope it helps.
James
-----Original Message-----
From: Kevin Crabb [mailto:kcrabb@stanford.edu]
Sent: Thursday, February 28, 2008 5:16 PM
To: labmembers@snf.stanford.edu
Subject: Ferric Chloride (FeCl3) Etch Mask?
Hello,
I'm hoping to etch patterns into/through copper, nickel, and/or aluminum
foils using an aqueous solution of FeCl3. I was wondering if anybody
has
any experience etching any metals with FeCl3, and which masks work for
this
process. Any help would be greatly appreciated! Thanks,
Kevin
kcrabb@stanford.edu
Special Ebeam Lab Presentation:
Chemically Amplified Molecular Resists for E-Beam Lithography
Dr. Alex P.G. Robinson University of Birmingham, UK.
Tuesday March 4, 2008 1:30 PM in CIS 101
Chemically Amplified Molecular Resists for E-Beam Lithography
J. Manyama, F.P. Gibbonsa, S. Diegolib, M. Manickamb, J.A. Preeceb, R.E. Palmera, A.P.G. Robinsona
aNanoscale Physics Research Laboratory, School of Physics and Astronomy, The University of Birmingham, Birmingham, B15 2TT, UK
phone: +44 (0)121 414 4641 e-mail: a.p.g.robinson@bham.ac.uk
bSchool of Chemistry, The University of Birmingham, Birmingham, B15 2TT, UK
Key words: Electron Beam Lithography, Molecular Resist, Fullerene, Chemically Amplified Resist
The minimum lithographic feature size for microelectronic fabrication continues to shrink, and resist properties are beginning to dominate the achievable resolution. There is a strong need for a high resolution, high sensitivity resist for the 32 nm node, and beyond, that is not met by conventional polymeric resists at this time. The line width roughness (LWR) requirements at the 32 nm node [1] are already equal to the radius of gyration of a typical resist polymer, [2] whilst the resolution itself will be less than the polymer molecule size at future nodes. Molecular resists, such as oglimers and molecular glasses rely on smaller molecules, giving the potential for lower LWR and improved resolution. Fullerene derivative molecules have a diameter of approximately 1 nm and have been shown to act as negative tone resists with high etch durability and a resolution of 10 nm when exposed via electron beam lithography. However, the sensitivity of such resists is extremely poor and significant improvements would have to be made to make the material commercially viable. A common way to improve resist sensitivity is chemical amplification (CA) by addition of a photosensitizer, and optionally a cross-linker. Here we present a fullerene based three component chemically amplified resist system, which shows high resolution and sensitivity, wide process latitude, and etch durability comparable with commercial novolac resists.
Fullerene resist films were prepared on hydrogen terminated silicon by spin coating and were irradiated using a Philips XL30SFEG scanning electron microscope equipped with a Raith lithography system. The fullerene CA resist consisted of the derivative MF03-04, an epoxide cross-linker and a photoacid generator. The sensitivity of this resist was shown to be between 5 and 10 µC/cm2 at 20 keV for various combinations of post application bake and post exposure bake conditions. Using 30 keV electron beam exposure, sparse patterns with 12 nm resolution were demonstrated, at a line dose of 300 pC/cm, whilst dense patterns with half-pitch 20 nm were achieved at 200 pC/cm, as shown in figure 1. The LWR for the densely patterned resist (measured at hp 25 nm) is approximately 4 nm. The etch durability of the fullerene resist was comparable to SAL601, a common novolac resist.
[1] International Technology Road map for Semiconductors, 2006 Update, http://www.itrs.net.
[2] R.L. Brainard, G.G. Barclay, E.H. Anderson, L.E. Ocola, Microelectron. Eng., 2002, 61-62, 707.
Figure 1: 20 nm half-pitch lines and spaces exposed with a dose of 200 pC/cm at 30 keV, developed in MCB (1:1) IPA for 10 s, with a 10 s IPA rinse.
In response to my question about where to get an HP 4145A fixed, several users
said they'd also like to know where to fix old HP equipment, so here's a summary
of the responses so far:
* One SNFer sent a 4195A to Tucker electronics in Texas.
* Another SNFer said OpLink Solutions in GA (www.oplinksolutions.com) supports the HP 4145A.
* Another SNFer has used Calwright for several pieces of older HP equipment, and thinks the
4145A "shouldn't be a problem for them."
* One SNFer said go to www.testlabco.com
* Finally, ever the comedian, Josh Ratchford said "I'll fix it for $100k."
As a side note, I priced out "new" HP 4145As, and they seem to go for $7.5-10k.
John
Eric
Calright Instruments
David Swanson
2232 Verus Street, Suite D
San Diego, CA 92154
USA
866.363.6634 Toll Free
619.374.7012 Fax
sales@calright.com
www.calright.com
-----Original Message-----
From: John Ross Jameson [mailto:jameson@stanford.edu]
Sent: Thursday, February 28, 2008 1:45 PM
To: labmembers@snf.stanford.edu
Subject: HP 4145A needs repair
Hi Labmembers,
I have a broken HP 4145A that I'd like to have repaired.
Does anyone know anyone who does this? HP and Agilent no
longer support the 4145A in any way. I'm hoping to find
a retired HP engineer, maybe even someone who worked on the
4145A itself back in the day.
Thanks,
John
try OpLink Solutions in GA (www.oplinksolutions.com). They support the
HP 4145a.
they recently rebuilt a HP LCR meter that I thought was beyond repair,
and at reasonable cost.
Best,
Mark
On Feb 28, 2008, at 1:44 PM, John Ross Jameson wrote:
> Hi Labmembers,
>
> I have a broken HP 4145A that I'd like to have repaired.
> Does anyone know anyone who does this? HP and Agilent no
> longer support the 4145A in any way. I'm hoping to find
> a retired HP engineer, maybe even someone who worked on the
> 4145A itself back in the day.
>
> Thanks,
> John
>
I have a broken HP 4145A that I'd like to have repaired.
Does anyone know anyone who does this? HP and Agilent no
longer support the 4145A in any way. I'm hoping to find
a retired HP engineer, maybe even someone who worked on the
4145A itself back in the day.
Thanks,
John
The next installment of the Process Grand Rounds will be Friday, 2/29,
at 11:30 in CIS 101. On the agenda:
1. Process issues anyone wishes to present (Maryam?) (10 min?)
2. Follow up on action items from previous Grand Rounds. (5 min)
3. Reports from each of the functional area "quality circles" regarding
the data each group would like collected and reported. John will not be
here, but Bill Murray will try to make it. It would also be valuable
for groups to share their proposals to come up with a somewhat unified
lab vision of what we'd like data collection and reporting to be.
4. Group discussion to determine the objectives/action items for the
next round of Quality Circle activities.
All labmembers are welcome. This time, pizza.
Your SNF staff
--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu
It's the end of an age for SNF.... where we say "goodbye" to
convenient, expert in-house maskmaking, reliable service against all
odds, and a solid presence in the lab...
Please join us as we say "goodbye" to.... the Micronics Laser
Maskwriter. At one pm today, Paul Jerabek will flip the four switches
that give life to this system. This is an end of an age.
Your SNF staff
--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu
Dear Labmembers,
I apologize for the last (blank) note.
Found Women’s Black Knit Sweater with Gray Piping on the bench outside the lab. This sweater has been sitting there for a couple of weeks. If this is your sweater please come to my cubicle # 41 to pick it up.
Thanks,
Maureen
Maureen Baran
Stanford Nanofabrication Facility
Lab Services Administrator
650-725-3664
Hyeun-Su Kim
Department of Mechanical Engineering
Adviser: Thomas W. Kenny
February 29st, 2008
8:30AM (Refreshments served at 8:15AM)
CIS-X Auditorium
"A Variable Thermal Resistor (VTR) for Low Power Temperature
Regulation of Chip-Scale Atomic Clock (CSAC)"
Abstract:
It is essential for a chip-scale atomic clock (CSAC) development to
make an efficient thermal isolation structure as well as to use low
power for temperature controlling due to the low-power requirements
(near 30mW total power consumption in the presence of -40~50°C of
ambient temperature variation). There have been several efforts on the
thermal management of a CSAC to keep the temperature of a vapor cell
in a CSAC at 75°C with low power using thermal isolation structures;
however, this is the first study that shows the ability of thermal
resistance change in multiple stages to control a CSAC temperature in
a range of ambient temperature variation. We developed a variable
thermal resistor (VTR) for the purpose of changing the thermal
resistance of a CSAC package according to the ambient temperature
variation.
The current VTR is comprised of thermal isolation structures
(polyimide posts) and an array of ten electrostatic actuators
(suspended gold beams). The top silicon die which has ground electrode
for vertical electrostatic actuator is separated by three 30um tall
polyimide posts. Ten 1.6um thick gold suspended beams are placed
between the top and the bottom dies while they keep the distance to
the top die 5±1um at zero bias. When 100V of electrical potential is
applied to the gold beams, they bend up and make contact with the top
die. As a consequence, the thermal resistance of VTR decreases. The
0.5um SiO2 passivation layer on the top die prevents electrical
contact between ground electrode and the gold beams.
In addition to the current design of VTR, we also discuss passive
actuation type VTR which is actuated by the ambient temperature
variation. An improved thermal resistance measurement method we have
developed is also introduced and evaluated.
The current version of VTR demonstrates thermal resistance variation
from 200°C/W to 1200°C/W with 100±20°C/W of resolution. As a room
temperature thermal switch that deals with low heat load, VTR may
serve as a high thermal resistance package solution for any low- power
and high-temperature electric device.
Just wanted to let you know -- there was a power glitch this morning
around 7:30 am. Most of you probably didn't notice it, since the
maintenance crew quickly descended on the lab and reset/checked
everything. The cause turns out to have been a downed 16 KV PG&E power
line. Please be aware that it is possible there may still be lasting
effects (lost recipes, for example) -- if you have any problems, log
them onto Coral and notify staff.
Thanks,
Mary
--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu
Bill Martin, who represents Compugraphics will be on campus this
week. He is holding a seminar along with a question and answer
session on Tuesday, Feb. 26th, beginning at 1pm in CIS101. This will
be an ideal time to stop in and learn the new procedure for having
mask made at Compugraphics. The objective, is by the end of the day,
to have a thorough understanding of the mask submission process,
beginning with the design requirements and ending with a mask in you hands.
Please join us with all of the mask making questions you might have.
Regards,
Ed
Appreciated your time and reply!
Thanks,
Jason
In order to attach two computer racks to the floor, we need to drill a
total of 8 holes in the concrete using the RotoHammer. While this
should be isolated from the lab by virtue of being on a separate
foundation, it could conceivably cause a bit of vibration. In order to
minimally inconvenience normal lab activiities .... not to mention the
folks that have offices near the first-floor communication closet ... we
will plan to do this early tomorrow morning (Tuesday, February 26)
starting at about 6 a.m. with the expectation of being completed by 7 a.m.
As a second item, Jim Kruger made the suggestion that it would be useful
to have some form of identification on the Sun Rays when reporting
problems related to keyboards, mice, etc. This is a good suggestion and
we have numbered each Sun Ray with a number from 1 to 25 that you can
use when reporting problems. For the Sun Ray 1s, this number is on the
body of the Sun Ray just above the slot where you insert a smart card.
Thank you for your continued support,
John
I am looking for short channel (< 1um) Si (single-crystal) MOSFET
devices (n-channel/p-channel enhancement mode). I prefer chip FETs to
packaged FETs if possible and would like to know the doping
concentration.
If you know and share the information of vendors and sources with me,
I really appreciate it.
Thanks,
Na Young
--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu
Leonard Chan reports that both DI pumps are not functional. He is
working on getting a functional one delivered and installed, with the
goal of having something in place and working by end of today. Stay
tuned for more.
SNF Staff
--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu
The building has run out of DI water. According to Facilities Ops, the
pump for the DI water system has failed The backup is in the process of
getting preventive maintenance and so is not online yet. FacOps is
working on this right now and will update us soon. In the meantime,
there is no DI water available. At SNF, all equipment requiring DI
water for operation has been shutdown.
Your SNF staff
--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu
Hi all,
Does anyone have experience with polycrystalline Cadmium (high purity)?
I am looking for coarse grained cadmium (about ~1mm size of grains) because I want to see some mechanical behaviors with different crystallographic orientations. It’s not easy for me to find cadmium ‘with coarse grain size’.
Thanks in advance,
Seok-Woo Lee
--
Seok-Woo Lee
Ph.D. Student, Department of Materials Science and Engineering
Stanford University
Peterson Building Room 554G
Stanford, CA 94305
-- Candace K. Chan Ph.D. Student, Department of Chemistry Stanford University McCullough Building Room 209 476 Lomita Mall Stanford, CA 94305
As part of our enterprise forum series, we are hosting a visit by Shahin Farschi, from Lux Capital. Following a brief presentation, Shahin is most interested in an informal discussion with researchers about the role of VC's in developing new opportunities. This is scheduled for Wednesday, March 5, from 4-5 pm in CIS 101. Shahin invites advance suggestions for specific topics of discussion -- just email him at the address below.
Shahin's talk will be on the following: The role of venture capital in the success of today's technology startups
Abstract: Ever-increasing market competition and narrow market windows further exacerbate the challenge of commercializing a novel semi/device technology. These circumstances have altered the relationship between investors and entrepreneurs, from one where investors are passive explorers of new opportunities presented by entrepreneurs, to one where entrepreneurs and investors work together to find a timely development path to a market that would best leverage an innovation. This seminar will introduce the audience to several examples of how venture investors can assist innovators at the very early stage, which will be followed by a Q&A session.
Background: Shahin Farshchi is an associate at Lux Capital, a venture capital firm that invests in early-stage semiconductor, energy, materials, and biotechnology companies, where he assists in the creation and evaluation of semiconductor and energy-related companies for investment. Shahin earned his B.S. from the University of California at
Berkeley, followed by his M.S. and Ph.D. degrees in Electrical Engineering with a focus on MEMS and analog IC design from the University of California at Los Angeles.
Shahin Farshchi, Ph.D.
Associate
Lux Capital Management, LLC
T: 925.323.2784
http://www.luxcapital.com
shahin.farshchi@luxcapital.com
--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang@stanford.edu
http://snf.stanford.edu
We were having a presentation in CIS-201 (the presentation room next
to Prof. Simon Wong's office) on Feb 8 (Friday). I accidentally left
the projector power chord in that room.
Please let me know if any one of you found the power chord.
thanks
-gaurav
650-704-1029
Prof. Nishi group
The bulk sodium hydroxide for the acid neutralization system has been
refilled and normal operations may now resume.
Thank you for your support,
John
I have just received word from FacOps that our supply of sodium
hydroxide that is used in the acid neutralization system is virtually
exhausted. The truck that will re-supply that tank should be arriving
this morning.
For the moment, however, we must ask that you not dump any acids this
morning until we send out the "all clear". Dumping of unneutralized
acid would cause us to be in violation of environmental waste regulations.
We apologize for this inconvenience but appreciate your support.
Thanks,
John
If you see a message like this one (CONFIRM YOUR SUNet EMAIL ACCOUNT) -
DON'T REPLY! It's a phishing expedition for your personal info. John
passed on a warning about this happening at other universities -- looks
like they're hitting Stanford now:
http://snf.stanford.edu/cgi-bin/ezmlm-cgi?mss:3036:200801:phkcedhhcfanjhglhamj
And always be careful about your personal info....
Your Coral staff
Minutes from the last Process Grand Rounds have been posted (linked from
the SNF home page.) For those in attendance, please let me know if
we've missed something or any other corrections that may be required.
The next SNF Process Grand Rounds will be Friday, 2/22, 11:30-1 pm, in
CIS 101. The main topic will be a planning meeting for what we're
calling "Superuser" and "Quality Circle" programs which grew out of
discussions that Prof. Nishi and several other faculty have had over the
past few weeks with concerned students about the state of the lab. The
objective of this meeting is to define a framework for labmembers to
become more involved and have more say in the lab operations -- and
better work with the SNF staff to set expectations and lab priorities.
All labmembers (and staff members) are welcome. But please be aware
that the core group of students who have met with Prof. Nishi have
already volunteered and invested much time in discussions with each
other, their PI's and staff about their ideas. We would like to make
this a productive meeting and so ask that anyone who attends should also
be prepared to participate and volunteer (no spectators, please!) And
we'd like to encourage everyone to talk with staff and each other -- and
bring constructive ideas to the table.
Looking forward to seeing you there!
Your SNF staff
Thanks,
~j
Another cell phone has been left behind in the ladies room, across from the Lab, on the first floor of the CIS building. If this is your phone, please stop by my cubicle. I will be leaving today at 5:00P today.
Maureen
Maureen Baran
Stanford Nanofabrication Facility
Lab Services Administrator
650-725-3664
This watch was found a couple of weeks ago and just handed in today. If you misplaced your watch between the CIS building and Ginzton Lab, please come by my cubicle, it’s number 41 on the first floor of the CIS building, closest to the doors that face the Applied Physics building.
Maureen
Maureen Baran
Stanford Nanofabrication Facility
Lab Services Administrator
650-725-3664
Xuefeng (Steve) Zhuang
Department of Electrical Engineering
Advisor: Professor Butrus T. Khuri-Yakub
Date: Tuesday, February 19, 2008
Time: 2 PM (Refreshments served at 1:45 PM)
Location: Packard room 202
Title: Capacitive Micromachined Ultrasonic Transducers (CMUTs) with
Through-Wafer Interconnects
Abstract:
Capacitive micromachined ultrasonic transducer (CMUT) technology is a
promising candidate for making 2D ultrasound transducer arrays for
applications such as 3D medical ultrasound, non-destructive evaluation
and chemical sensing. Advantages of CMUTs over traditional
piezoelectric transducers include low-cost batch fabrication, wide
bandwidth, and ability to fabricate arrays with broad operation
frequency range and different geometric configurations on a single
wafer. When incorporated with through-wafer interconnects, a CMUT
array can be directly integrated with front-end IC to mitigate the
effects of the parasitic capacitance from the connection cables.
Through-wafer via is the existing interconnect scheme for 2D CMUT
arrays, and many other types of MEMS devices. However, efforts to
integrate the direct fusion bonding process with through-wafer via
interconnects have been unsuccessful. The interconnect fabrication
steps degrade the surface conditions of the wafer, making it difficult
to bond.
In this talk I present a new through-wafer interconnect technique that
is compatible with MEMS device fabrication in general, including both
the surface-micromachining and the direct fusion bonding processes.
The new technique uses through-wafer trenches to separate array
elements and utilizes the silicon substrate as the conductive
electrode. Two exemplary implementations incorporating CMUT arrays
are presented, one with a carrier wafer and the other with a built-in
silicon frame structure for mechanical support. Both implementations
reduce fabrication complexity compared to the through-wafer via
process, and result in low series resistance and small parasitic
capacitance. 2D CMUT arrays integrated with trench-isolated
interconnects show high output pressure (2.9 MPa), wide bandwidth
(95%), small pulse-echo amplitude variation (sigma = 6.6%), and
excellent yield (100%). An important added benefit of the
trench-isolated interconnect is the capability to realize flexible
arrays, which is also discussed in the presentation. I will also
demonstrate 3D ultrasound imaging based on a trench-isolated 2D array
integrated with an IC.
The Sunrays and the SNF Mail Server/Web Site will be down early Sunday
morning for a period of several hours starting at about 4:30 a.m. The
purpose of this downtime will be to move home directories to a new file
system that will:
1. Provide somewhat more disk space so that we are not so close to 100%
on the /home/User partition (once again we are hovering between 99% and
100% on that system).
2. Allow us to increase the size of that partition "on the fly" if/when
we need to do so in the future.
3. Provide better redundancy in the event of a disk crash.
4. Provide somewhat faster performance.
To do this, however, we have to shutdown key systems so that incoming
mail messages, browser caches, and file edits do not thwart our attempts
to synchronize the old file system with the new file system.
So, starting in the very early hours on Sunday morning, the Sunrays in
the lab, the SNF mail system, and the SNF web site will be down for what
I expect to be a period of several hours while we move/synchronize these
file systems.
During that time, Remote Coral should be available the entire time.
Also, I will be available either in CIS 220 or my office (CIS 129,
x5-3715) in case you need to contact me to enable or disable a tool.
The Coral servers will be fully functional during that time.
We apologize for this inconvenience but hope that this has been schedule
so as to provide minimal disruption.
Thank you for your continued support,
John
X-Sieve: CMU Sieve 2.3
Delivered-To: rissman@stanford.edu
Delivered-To: rissman@snf.stanford.edu
From: "Leonard Chan" <leonardc@bonair.stanford.edu>
To: <rissman@snf.stanford.edu>, <mtang@snf.stanford.edu>,
<shott@snf.stanford.edu>, "Ted Barg" <tberg@snf.stanford.edu>,
"Ed Myers" <edmyers@stanford.edu>
Subject: FW: Tomorrows inspection is a go
Date: Fri, 15 Feb 2008 07:14:50 -0800
X-Mailer: Microsoft Outlook IMO, Build 9.0.6604 (9.0.2911.0)
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To All,
FYI.... the final County acceptance test for the phase 1 TGO project will be done today.
Thanks,
Leonard
-----Original Message-----
From: David Boyanich [ mailto:dboy@facilities-dynamics.us]
Sent: Thursday, February 14, 2008 3:43 PM
To: Leonard Chan
Cc: Aaron McCarthy
Subject: Tomorrows inspection is a go
Leonard,
I just confirmed with Rob Campbell of the County Fire Marshalls office that we will still have an inspection at 9:00 am. Please have a printed copy of the full test report that was performed in December, and a printed copy of the current Matrix. I will arrive around 8:00 to prepare.
Best regards,
David Boyanich
Managing Partner
Facilities Dynamics, Inc.
Cell Phone: (408) 690-5357
