Re: Pt and TiN etch qestions

Henry,
The Pt etching process which came with the PQ is as follows:

10C, 30sccm Ar, 10 sccm Cl2, 1.0 mT, 600w uw power, -300V bias, 10T backside He
Pt etch rate of 450A/min, PR rate of 950A/min.

1 mT is a bit low for our tool. A high bias voltage above 150V is critical for a sputter etch bias. You will not get a higher enough voltage at 50 W of bias power. Because a modification to wafer clamp mechanism done years ago, it is difficult to get high bias voltages on our tool, and if you try by using high bias powers, you will likely damage the springs in the clamp mechanism. Another comment is that lower pressure give higher bias voltages.

Jim

----- Original Message -----
From: "jim kruger" <jimkruger@yahoo.com>
To: "zhangll ime" <zhangll.ime@gmail.com>, "Henry Hong-Yu Chen" <hongyuc@stanford.edu>
Cc: labmembers@snf.stanford.edu
Sent: Friday, May 4, 2012 2:29:48 PM
Subject: Re: Pt and TiN etch qestions



If you wish to try this in PQuest at SNF, I strongly recommend (= insist) that you use 5 mTorr pressure. 10 and above result in a "hard to see" instability that forms a fireball up at the microwave window which has no cooling.

Higher RF (100 w?) will etch faster, please record the DC bias.



Please publish any results.


jim






From: "zhangll.ime@gmail.com" <zhangll.ime@gmail.com>
To: Henry Hong-Yu Chen <hongyuc@stanford.edu>
Cc: "labmembers@snf.stanford.edu" <labmembers@snf.stanford.edu>
Sent: Friday, May 4, 2012 1:19 PM
Subject: Re: Pt and TiN etch qestions

For Pt RIE etch:

Ar: 40sccm,
Cl2: 40sccm
Pressure: 10mTorr
RF pow 50W
ECR pow 700W
Rate:30nm/min

This recipe works at MIT, but i haven't got a chance to try it in out cleanroom.

Good luck!

Sincerely yours,
Liangliang

On May 4, 2012, at 2:57 PM, Henry Hong-Yu Chen < hongyuc@stanford.edu > wrote:

> Dear Lab Members,
>
> My colleague and I are trying to etch through the following structures
> by dryetch (P5000? PQUEST?). I wonder if anyone can share the
> experience/recipe with us. Both structure are on the top of very
> thick SiO2.
>
> Top/Bottom => 50nm SiO2 (STS) / 30nm Pt (innotec)
> Top/Bottom => 50nm SiO2 (STS) / 80nm TiN (AJA)
>
> Thanks,
> Henry