In my process, I'm using SPR 955 to pattern 250nm PECVD SiO2 with dry etch in the MRC.
I'm getting great, vertical sidewalls -- which is normally desirable. But in my next step (reactive sputtering of a dielectric), I'm getting uneven coverage at the corners, which is shorting my devices.
I think this can be solved by using a more isotropic etch. Wet etch leaves undesirable residue on my Pt etch stop, so I would like to stick with dry etch. Is there a technique to get slightly more isotropic etches or a graded sidewall of some kind? I am considering trying:
- Higher pressure during dry etch
- Not using HMDS so that the resist delaminates a little at the edges
- Not curing/baking the resist before my dry etch
Any tips would be most appreciated. Thanks in advance.
--
Mihir Tendulkar
Applied Physics PhD Candidate
Nishi Group, Stanford University
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