PhD Oral Examination - Saeroonter Oh, Friday, May 28, 2010, 10:00AM

Stanford University EE PhD Oral Examination

 

Modeling of III-V FETs for Beyond-22nm Logic Circuits

 

Speaker: Saeroonter Oh

Advisor: Professor H.-S. Philip Wong

 

Department of Electrical Engineering, Stanford University

Date: Friday, May 28, 2010

Time: 10 AM (Refreshments served at 9:45AM)

Location: Paul Allen Auditorium (CISX-101)

  

Abstract

  For beyond-22nm CMOS technology, III-V FETs are considered a compelling candidate for extending the device scaling limit of low-power and high-speed operation, owing to their superb carrier transport properties and recent experimental advancements. In this talk, device modeling and circuit analysis are used to study the key considerations for III-V logic circuits to be viable. One of the requirements for VLSI logic is device density. A study on device footprint scaling and the impact of parasitic elements on circuit performance is presented. A physics-based compact model for III-V FETs is introduced for accurate circuit-level performance estimation and digital circuit design. The model encompasses effects essential for logic applications that are not generally considered in other III-V models, such as field-dependent quasi-ballistic ratios, trapezoidal quantum-well energies, and capacitances with 2D potential information. We apply the compact model in various circuit environments to demonstrate the capability of the model and also to project performance and power trends for beyond-22nm technology. In particular, we study the circuit performance of sub-22nm SRAM circuits using III-V MOSFETs with high-k dielectrics and propose a minimum requirement for the III-V PMOS strength for All-III-V SRAM to be viable.