Phd Orals: Sarves Verma, February 10th, 1:00 pm, CISX Auditorium

Tunnel Barrier Engineering for Flash Memory Technology

Sarves Verma

Advisor: Professor Krishna Saraswat
Department of Materials Science & Engineering
Department of Electrical Engineering

Wednesday, February 10th, 2010, 1:00 pm
CISX Auditorium
(Refreshments served at 12:45pm)

Abstract

The conventional Flash memory faces two critical obstacles in the future: Density and Voltage scaling. Density is associated with scaling the gate length. The gate length cannot be reduced beyond a point because it requires a commensurate gate stack, specifically, tunnel oxide scaling for maintaining good gate control and short channel effects. However, the gate-tunnel oxide (GTO) reduction has a practical lower bound of ~ 7-9nm (depending upon NAND or NOR) due to leakage and data retention constraints. Below this GTO thickness, irrespective of how inter-poly dielectric (referred as ONO) is scaled, the electric field across it during charge retention increases, leading to unacceptable levels of tunneling current. The second major challenge with scaling is to reduce the programming and erase operation voltages. The usual operation voltages for these processes are much greater (15-18 Volts). With scaling, it is imperative for operating voltages to reduce. Typically, read voltages are low, while erase and program operations stress the charge pump requirements and dictate the maximum voltages. The major impediment in erase voltage scaling is, once again, the inability to scale the gate oxide. Recently, engineered tunnel barriers were proposed as solutions to scaling gate oxide. It is postulated that engineered barriers offer faster program/erase yet maintain excellent retention. However, a detailed characterization of engineered tunnel dielectrics and a deeper understanding of the erase/program mechanism are sought to establish its implementation.
In the first half of the talk, we perform simulations to establish the feasibility of tunnel barriers under Flash memory device constraints. We look at different higher-K materials as a replacement for SiO2 and perform global optimization over different materials. This is first done under absence of traps in these materials. Later the assumptions are relaxed and traps are incorporated in these materials. In the second part of the talk, we implement engineered tunnel barriers based on the simulation results. However, it is observed that presence of traps in these materials degrades performance. Retention loss and endurance degradation are identified as two major problems, hindering implementation and scaling. In the third and final part, we discuss solutions to these problems. Fluorine is well known as a passivating agent for traps in high-K dielectrics. We incorporate fluorine in engineered tunnel stacks and show electrical & physical characterization results to emphasize its advantages. Finally, alternative tunnel barrier structures and materials are discussed to continue scaling of gate dielectrics.