PhD Oral Exam - Lan Wei, Monday, February 22, 2010; 10:00 am

--
EE students mailing list
ee-students@lists.stanford.edu
https://mailman.stanford.edu/mailman/listinfo/ee-students

 

Lan Wei

Advisor: H.-S. Philip wong

Time: 10am (Refreshment at 9:45am)

Date: Feb 22 (Mon), 2010

Location: Paul Allen Building Auditorium (CIS-X Aud)

 

Nanoelectronics: Technology Assessment and Projection at the Device, Circuit, and System Level

Abstract:

Nowadays, physical gate length can no longer be effectively scaled down and traditional boosters (e.g., strain, high-k/metal gate) are exhibiting diminishing returns on performance improvement.  Continued progress in nanoelectronics necessitates a holistic view across the boundaries of device, circuit and system domains. The best devices are those that are optimized for the circuits and systems of the target application.  Device design and engineering must aim at improvements at the circuit and system levels.  At the same time, new applications in various areas, such as life-science, are enabled by emerging technology.

In this talk, the design space is explored for future Si CMOS technology and for carbon nanotube field effect transistors, a promising technology in the post-Si era.  Compact models for transport properties and capacitive components of different device structures have been developed to facilitate circuit-level analysis and system-level optimization.  Possible ways of extending the technology roadmap are proposed.  We propose scenarios of selective device structure scaling that will enable Si CMOS technology scaling for several generations beyond the currently perceived limits.  Beyond Si CMOS scaling, carbon nanotube field effect transistors (CNFETs) are optimized and projected to achieve 5x chip-level speed up over PDSOI at 11 nm technology node for a high-performance four-core processor with 1.5M logic gates and 5MB SRAM per core.