EE PhD Oral Examination - Albert Lin, Friday, February 12, 2010; 3:30pm

Carbon Nanotube Devices and Circuits

Speaker: Albert Lin, Department of Electrical Engineering
Advisor: Professor H.-S. Philip Wong
Associate Advisor: Professor Subhasish Mitra

Date: Friday, February 12, 2010
Time: 3:30PM
Location: Packard 202

Abstract

Carbon Nanotube Field Effect Transistor (CNFET) technology has
received a lot of attention in the past few years as a promising
candidate for future integrated circuits, due in part to its potential
for ballistic transport and excellent intrinsic delay. However, to
realize the potential of CNFETs, carbon nanotube (CNT) technologies
that are scalable and robust must be developed. Such scalable carbon
nanotube technologies are presented here, from carbon nanotube
material synthesis to circuit fabrication.

In particular, four main achievements are discussed: (1) Wafer-scale
aligned CNT growth, delivering high-density, "nearly-perfectly"
straight CNTs; (2) Wafer-scale CNT Transfer, enabling independent
optimization of growth and device fabrication processes; (3) VLSI-
compatible device and circuit fabrication, achieving repeatable and
reliable wafer-scale integration; and (4) ACCNT (pronounced as
"accent"), a VLSI-compatible metallic-CNT tolerant design methodology,
achieving robust circuits despite imperfect CNT materials. Using these
techniques, CNT transistors, inverters, NANDs, and other logic gates
and small circuits are experimentally demonstrated. These four
contributions propel carbon nanotube technology forward towards the
vision of robust large-scale carbon nanotube circuits.