EE310 Seminar: Ge MOSFETs for High Performance CMOS Applications

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EE310 Seminar
Date: Tuesday, January 26, 2010
Time: 4:15 - 5:05 pm
Place: Hewlett 102
Host: Prof. Yoshio Nishi

Title: Ge MOSFETs for High Performance CMOS Applications

Speaker: Dr. Duygu Kuzum, Stanford University

Abstract:
As the semiconductor industry approaches the limits of traditional silicon
CMOS scaling, introduction of performance boosters like novel materials and
innovative device structures has become necessary for the future of CMOS.
High mobility materials are being considered to replace Si in the channel to
achieve higher drive currents and switching speeds. Ge has particularly
become of great interest as a channel material, owing to its high bulk hole
and electron mobilities. However, replacement of Si channel by Ge requires
several critical issues to be implemented in Ge MOS technology. High quality
gate dielectric for surface passivation, low parasitic source/drain
resistance and performance improvement in Ge NMOS are among the major
challenges in realizing Ge CMOS.
Direct formation of a high-k dielectric on Ge has not given good results in
the past. A good quality interface layer is required before the deposition
of a high-K dielectric. In this talk, we will present our technique to
engineer Ge/insulator interface. Characterization of gate dielectric/channel
interface and a deeper understanding of mobility degradation mechanisms in
Ge MOSFETs will be discussed. Ge N-MOSFETs have exhibited poor drive
currents and low mobility, as reported by several different research groups
worldwide. In spite of the increasing interest in Ge, the major mechanisms
behind poor Ge NMOS performance have not been completely understood yet.
Detailed characterizations are performed to identify the mechanisms behind
poor Ge NMOS performance in the past. Record high mobility exceeding Si
universality has been demonstrated for Ge NMOS devices fabricated with the
ozone-oxidation and the low temperature S/D activation processes. Novel
source/drain formation processes and strained-Ge architectures for nanoscale
Ge MOSFETs will be presented in the last part of the talk.

Biography:

Duygu Kuzum received her B. S. in Electrical Engineering from Bilkent
University, Turkiye, in 2004 and Ph.D. in Electrical Engineering from
Stanford University in 2009. She is currently a postdoctoral researcher in
Prof. H. -S. Philip Wong in Stanford Nanoelectronics Group. Her Ph.D.
research focused on design, fabrication and characterization of Ge MOSFETs
for future technology nodes. She is currently working on novel memory and
storage devices and nanoscale electronic devices for nano-bio applications.
She worked as a research intern at Translucent Inc. (2006) and Intel
Component Research (2008). She was a recipient of a number of awards,
including Texas Instruments Fellowship and Intel Foundation Fellowship.