PhD Orals - Nishant Patil, June 8, 2009, 3:30 pm, Packard 101

Reminder - Ph.D. Orals

 

Carbon Nanotube Digital VLSI Circuits

 

Nishant Patil

Advisor: Subhasish Mitra

Department of Electrical Engineering

Stanford University

 

Time: 3:30 pm (refreshments served at 3:15 pm)

Date: Monday, June 8, 2009

Location: Packard 101

 

Abstract

 

Carbon Nanotube Field Effect Transistors (CNFETs), consisting of semiconducting single walled Carbon Nanotubes (CNTs), have several promising applications such as extensions to silicon VLSI and large area electronics. While there has been significant progress at a single-device level, a major gap exists between such results and their transformation into VLSI CNFET technologies. Major CNFET technology challenges include mis-positioned CNTs, metallic CNTs, and wafer-scale integration. This work presents design and processing techniques to overcome these challenges. Experimental results demonstrate the effectiveness of the presented techniques.

 

Mis-positioned CNTs can result in incorrect logic functionality of CNFET circuits. A new layout design technique produces CNFET circuits for arbitrary logic functions that are immune to a large number of mis-positioned CNTs. This technique is significantly more efficient compared to traditional defect- and fault-tolerance techniques. Furthermore, it is VLSI-compatible and does not require changes to existing VLSI design and manufacturing flows.

 

A CNT can be semiconducting or metallic depending upon the arrangement of carbon atoms. Typical CNT synthesis techniques yield ~33% metallic CNTs. Metallic CNTs create source-drain shorts in CNFETs resulting in excessive leakage (Ion/Ioff < 5) and highly degraded noise margins. A new technique, VLSI-compatible Metallic-CNT Removal (VMR), overcomes challenges posed by metallic CNTs by combining layout design with CNFET processing. VMR produces CNFET circuits with Ion/Ioff in the range of 10^3-10^5, and overcomes the limitations of existing metallic-CNT removal approaches.

 

The above techniques are demonstrated for complex logic structures using wafer-scale growth and transfer of aligned CNTs. Such an integrated approach enables experimental demonstration of cascaded CNFET logic circuits.