Jin-Hong Park's University Oral Exam

Ph.D Dissertation Defense; “Physics and Technology of Low Temperature Germanium MOSFETs for Monolithic Three Dimensional Integrated Circuits”

 

Jin-Hong Park / Advisor: Prof. Krishna C. Saraswat / Dept. of Electrical Engineering

Date : 3pm (Refreshments served at 2:30 pm) on 26^th May @ location : CISX auditorium

 

As the minimum feature size of silicon (Si) CMOS devices shrinks to the nanometer regime, device behavior becomes increasingly complex, due to new physical phenomena at short dimensions and fundamental limitations in material properties are reached. One of the techniques that shows promise to overcome this obstacle is the utilization of monolithic three-dimensional integrated circuits (3D-ICs). By stacking devices vertically, it is expected that (1) more functionality can fit into a smaller space and (2) the signal delay and power consumption in the interconnect layers will decrease and bandwidth will increase. The major challenge in fabricating monolithic 3D-ICs is the maximum process temperature limit of 400 ºC in the upper layers of CMOS device processing, due to the fact that higher process temperature would destroy the underlying device and interconnect layers.

1. Single crystalline GeOI growth technique at below 360 ºC

First, we have investigated Ni or Au-induced crystallization and lateral crystallization of planar amorphous germanium (α-Ge) on SiO₂ at 360 ºC without the deleterious effects of thermally induced self-nucleation. Subsequently, single crystalline Ge growth has been achieved on SiO₂ by making dimension of α-Ge line smaller than the size of grains formed using Ni and Au-induced lateral crystallization at 360 ºC.

2. Low temperature dopants activation technique in Ge

Second, we have investigated low temperature boron and phosphorus activation in α-Ge using the metal-induced crystallization technique. Eight candidates of metals including Pd, Cu, Ni, Au, Co, Al, Pt, and Ti are used to crystallize α-Ge at low temperatures followed by resistivity measurement, TEM, and XRD analyses, thereby revealing behaviors of the metal-induced dopants activation process where metals react with α-Ge at a low temperature. It is found that Co achieves the highest B and P activation ratio in Ge below 360 ^oC with slow diffusion rate. The feasibility of low temperature activation technique has been demonstrated for a Ge gate electrode in a Si P-MOSFET using Schottky Ni (or Co) silicide source/drain.

3. High performance and low temperature Ge CMOS technology

Third, we demonstrate high performance n⁺/p & p⁺/n junction diodes and N & P-channel Ge MOSFETs, where Ge is heteroepitaxially grown on a Si substrate at sub 360 ºC and the low temperature gate stack comprises of Al/Al₂O₃/GeO₂. Shallow (~100 nm) source/drain junctions with very low series resistivity [5.2×10^-4 Ω-cm (in n⁺/p junction) and 1.07×10^-3 Ω-cm (in p⁺/n junction) at the lowest point of SRP] and high degree of dopant activation are achieved by Co-induced dopant activation technique. Consequently, high diode and transistor current on/off ratios (~1.1×10⁴ & ~1.13×10³ for N-MOSFETs and ~2.1×10⁴ & ~1.09×10³ for P-MOSFETs) were obtained in these N & P-channel Ge MOSFETs.

These low temperature processes can be utilized to fabricate Ge CMOS devices on upper layers in three-dimensional integrated circuits, where low temperature processing is critical.